Lines Matching +full:1 +full:eb
15 #address-cells = <1>;
16 #size-cells = <1>;
46 #address-cells = <1>;
72 intel,ixp4xx-eb-write-enable = <1>;
82 ide@1,0 {
89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
94 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
95 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
96 intel,ixp4xx-eb-mux-address-and-data = <0>;
97 intel,ixp4xx-eb-ahb-split-transfers = <0>;
98 intel,ixp4xx-eb-write-enable = <1>;
99 intel,ixp4xx-eb-byte-access = <1>;
101 reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
118 #interrupt-cells = <1>;
121 /* IDSEL 1 */
122 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
123 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
124 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
125 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
127 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
132 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
137 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
152 #address-cells = <1>;
159 phy1: ethernet-phy@1 {
160 reg = <1>;