dts/hisilicon/hi3519.dtsi

1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/hi3519-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 	#address-cells = <1>;
10 	#size-cells = <1>;
14 		#address-cells = <1>;
15 		#size-cells = <0>;
19 			compatible = "arm,cortex-a7";
24 	gic: interrupt-controller@10300000 {
25 		compatible = "arm,cortex-a7-gic";
26 		#interrupt-cells = <3>;
27 		interrupt-controller;
32 		compatible = "fixed-clock";
33 		#clock-cells = <0>;
34 		clock-frequency = <3000000>;
37 	crg: clock-reset-controller@12010000 {
38 		compatible = "hisilicon,hi3519-crg";
39 		#clock-cells = <1>;
40 		#reset-cells = <2>;
45 		#address-cells = <1>;
46 		#size-cells = <1>;
47 		compatible = "simple-bus";
48 		interrupt-parent = <&gic>;
56 			clock-names = "uartclk", "apb_pclk";
65 			clock-names = "uartclk", "apb_pclk";
74 			clock-names = "uartclk", "apb_pclk";
83 			clock-names = "uartclk", "apb_pclk";
92 			clock-names = "uartclk", "apb_pclk";
102 			clock-names = "apb_pclk";
112 			clock-names = "apb_pclk";
122 			clock-names = "apb_pclk";
126 		spi_bus0: spi@12120000 {
131 			clock-names = "sspclk", "apb_pclk";
132 			num-cs = <1>;
133 			#address-cells = <1>;
134 			#size-cells = <0>;
138 		spi_bus1: spi@12121000 {
143 			clock-names = "sspclk", "apb_pclk";
144 			num-cs = <1>;
145 			#address-cells = <1>;
146 			#size-cells = <0>;
150 		spi_bus2: spi@12122000 {
155 			clock-names = "sspclk", "apb_pclk";
156 			num-cs = <1>;
157 			#address-cells = <1>;
158 			#size-cells = <0>;
162 		sysctrl: system-controller@12020000 {
163 			compatible = "hisilicon,hi3519-sysctrl", "syscon";
168 			compatible = "syscon-reboot";