dts/broadcom/bcm2837.dtsi

2 #include "bcm2835-common.dtsi"
10 		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 		local_intc: interrupt-controller@40000000 {
13 			compatible = "brcm,bcm2836-l1-intc";
15 			interrupt-controller;
16 			#interrupt-cells = <2>;
17 			interrupt-parent = <&local_intc>;
21 	arm-pmu {
22 		compatible = "arm,cortex-a53-pmu";
23 		interrupt-parent = <&local_intc>;
27 	timer {
28 		compatible = "arm,armv7-timer";
29 		interrupt-parent = <&local_intc>;
34 		always-on;
38 		#address-cells = <1>;
39 		#size-cells = <0>;
40 		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
42 		/* Source for d/i-cache-line-size and d/i-cache-sets
43 		 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
44 		 * /about-the-l1-memory-system?lang=en
46 		 * Source for d/i-cache-size
47 		 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
51 			compatible = "arm,cortex-a53";
53 			enable-method = "spin-table";
54 			cpu-release-addr = <0x0 0x000000d8>;
55 			d-cache-size = <0x8000>;
56 			d-cache-line-size = <64>;
57 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
58 			i-cache-size = <0x8000>;
59 			i-cache-line-size = <64>;
60 			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
61 			next-level-cache = <&l2>;
66 			compatible = "arm,cortex-a53";
68 			enable-method = "spin-table";
69 			cpu-release-addr = <0x0 0x000000e0>;
70 			d-cache-size = <0x8000>;
71 			d-cache-line-size = <64>;
72 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
73 			i-cache-size = <0x8000>;
74 			i-cache-line-size = <64>;
75 			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
76 			next-level-cache = <&l2>;
81 			compatible = "arm,cortex-a53";
83 			enable-method = "spin-table";
84 			cpu-release-addr = <0x0 0x000000e8>;
85 			d-cache-size = <0x8000>;
86 			d-cache-line-size = <64>;
87 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
88 			i-cache-size = <0x8000>;
89 			i-cache-line-size = <64>;
90 			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
91 			next-level-cache = <&l2>;
96 			compatible = "arm,cortex-a53";
98 			enable-method = "spin-table";
99 			cpu-release-addr = <0x0 0x000000f0>;
100 			d-cache-size = <0x8000>;
101 			d-cache-line-size = <64>;
102 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 			i-cache-size = <0x8000>;
104 			i-cache-line-size = <64>;
105 			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
106 			next-level-cache = <&l2>;
109 		/* Source for cache-line-size + cache-sets
111 		 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
112 		 * Source for cache-size
113 		 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
115 		l2: l2-cache0 {
117 			cache-unified;
118 			cache-size = <0x80000>;
119 			cache-line-size = <64>;
120 			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
121 			cache-level = <2>;
126 /* Make the BCM2835-style global interrupt controller be a child of the
127  * CPU-local interrupt controller.
130 	compatible = "brcm,bcm2836-armctrl-ic";
132 	interrupt-parent = <&local_intc>;
137 	coefficients = <(-538)	412000>;
142 	compatible = "brcm,bcm2837-thermal";