dts/broadcom/bcm2836.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 		local_intc: interrupt-controller@40000000 {
14 			compatible = "brcm,bcm2836-l1-intc";
16 			interrupt-controller;
17 			#interrupt-cells = <2>;
18 			interrupt-parent = <&local_intc>;
22 	arm-pmu {
23 		compatible = "arm,cortex-a7-pmu";
24 		interrupt-parent = <&local_intc>;
28 	timer {
29 		compatible = "arm,armv7-timer";
30 		interrupt-parent = <&local_intc>;
35 		always-on;
39 		#address-cells = <1>;
40 		#size-cells = <0>;
41 		enable-method = "brcm,bcm2836-smp";
43 		/* Source for d/i-cache-line-size and d/i-cache-sets
44 		 * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
45 		 * /About-the-L1-memory-system?lang=en
47 		 * Source for d/i-cache-size
53 			compatible = "arm,cortex-a7";
55 			clock-frequency = <800000000>;
56 			d-cache-size = <0x8000>;
57 			d-cache-line-size = <64>;
58 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
59 			i-cache-size = <0x8000>;
60 			i-cache-line-size = <32>;
61 			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
62 			next-level-cache = <&l2>;
67 			compatible = "arm,cortex-a7";
69 			clock-frequency = <800000000>;
70 			d-cache-size = <0x8000>;
71 			d-cache-line-size = <64>;
72 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
73 			i-cache-size = <0x8000>;
74 			i-cache-line-size = <32>;
75 			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
76 			next-level-cache = <&l2>;
81 			compatible = "arm,cortex-a7";
83 			clock-frequency = <800000000>;
84 			d-cache-size = <0x8000>;
85 			d-cache-line-size = <64>;
86 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
87 			i-cache-size = <0x8000>;
88 			i-cache-line-size = <32>;
89 			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
90 			next-level-cache = <&l2>;
95 			compatible = "arm,cortex-a7";
97 			clock-frequency = <800000000>;
98 			d-cache-size = <0x8000>;
99 			d-cache-line-size = <64>;
100 			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
101 			i-cache-size = <0x8000>;
102 			i-cache-line-size = <32>;
103 			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
104 			next-level-cache = <&l2>;
107 		/* Source for cache-line-size + cache-sets
108 		 * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System
109 		 * /About-the-L2-Memory-system?lang=en
110 		 * Source for cache-size
113 		l2: l2-cache0 {
115 			cache-unified;
116 			cache-size = <0x80000>;
117 			cache-line-size = <64>;
118 			cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
119 			cache-level = <2>;
124 /* Make the BCM2835-style global interrupt controller be a child of the
125  * CPU-local interrupt controller.
128 	compatible = "brcm,bcm2836-armctrl-ic";
130 	interrupt-parent = <&local_intc>;
135 	coefficients = <(-538)	407000>;
140 	compatible = "brcm,bcm2836-thermal";