Lines Matching +full:0 +full:x3e000000
22 ranges = <0 0x34000000 0x102f83ac>;
28 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
33 reg = <0x01001f00 0x24>;
38 reg = <0x01003000 0x524>;
51 reg = <0x01006000 0x1c>;
60 ranges = <0 0x3e000000 0x0001c070>;
64 uartb: serial@0 {
66 reg = <0x00000000 0x118>;
76 reg = <0x00001000 0x118>;
86 reg = <0x00002000 0x118>;
96 reg = <0x00016000 0x70>;
99 #size-cells = <0>;
106 reg = <0x00017000 0x70>;
109 #size-cells = <0>;
116 reg = <0x00018000 0x70>;
119 #size-cells = <0>;
126 reg = <0x0001c000 0x70>;
129 #size-cells = <0>;
138 ranges = <0 0x3e300000 0x01c02000>;
144 reg = <0x00e20000 0x10000>;
155 reg = <0x00e30000 0x28>;
156 #phy-cells = <0>;
162 reg = <0x00e80000 0x801c>;
170 reg = <0x00e90000 0x801c>;
178 reg = <0x00ea0000 0x801c>;
186 reg = <0x00eb0000 0x801c>;
204 #clock-cells = <0>;
210 #clock-cells = <0>;
216 #clock-cells = <0>;
222 #clock-cells = <0>;
228 #clock-cells = <0>;
234 #clock-cells = <0>;
240 #clock-cells = <0>;
246 #clock-cells = <0>;
252 #clock-cells = <0>;
258 #clock-cells = <0>;
264 #clock-cells = <0>;
270 #clock-cells = <0>;
276 #clock-cells = <0>;
282 #clock-cells = <0>;
288 #clock-cells = <0>;
295 reg = <0x35001000 0x0f00>;
302 reg = <0x35002000 0x0f00>;
309 reg = <0x3e011000 0x0f00>;
322 reg = <0x3f001000 0x0f00>;