Lines Matching +full:0 +full:x60000
17 reg = <0x80000000 0x20000000>;
27 reg = <0x98000000 0x04000000>; /* 64M */
33 reg = <0x9f000000 0x01000000>; /* 16M */
37 size = <0x01000000>;
38 alignment = <0x01000000>;
44 size = <0x02000000>; /* 32MM */
45 alignment = <0x01000000>;
74 gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>;
75 linux,code = <ASPEED_GPIO(N, 0)>;
119 gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
178 #size-cells = <0>;
181 clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
182 data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
184 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
190 io-channels = <&dps 0>;
237 flash@0 {
247 u-boot@0 {
248 reg = < 0 0x60000 >;
252 reg = < 0x60000 0x20000 >;
256 reg = < 0x80000 0x1F80000 >;
272 u-boot@0 {
273 reg = < 0 0x60000 >;
277 reg = < 0x60000 0x20000 >;
281 reg = < 0x80000 0x1F80000 >;
291 pinctrl-0 = <&pinctrl_spi1_default>;
293 flash@0 {
305 pinctrl-0 = <&pinctrl_txd1_default
319 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
335 pinctrl-0 = <&pinctrl_rmii1_default>;
356 reg = <0x77>;
362 reg = <0x52>;
364 #size-cells = <0>;
369 reg = <0x76>;
370 #io-channel-cells = <0>;
375 reg = <0x60>;
377 #size-cells = <0>;
382 gpio@0 {
383 reg = <0>;
465 reg = <0x68>;
470 reg = <0x69>;
479 reg = <0x4c>;
484 reg = <0x70>;
489 reg = <0x71>;
499 reg = <0x4c>;
504 reg = <0x70>;
509 reg = <0x71>;
518 reg = <0x4a>;
535 reg = <0x60>;
537 #size-cells = <0>;
550 gpio@0 {
551 reg = <0>;
633 reg = <0x32>;
638 reg = <0x51>;
643 reg = <0x64>;
671 pinctrl-0 = <&pinctrl_wdtrst1_default>;