Lines Matching +full:0 +full:x60000
17 reg = <0x80000000 0x20000000>;
27 reg = <0x98000000 0x04000000>; /* 64M */
31 size = <0x01000000>;
32 alignment = <0x01000000>;
61 gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>;
62 linux,code = <ASPEED_GPIO(N, 0)>;
73 gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
74 linux,code = <ASPEED_GPIO(I, 0)>;
148 gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
190 gpios = <&pca1 0 GPIO_ACTIVE_LOW>;
205 #size-cells = <0>;
211 enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
217 io-channels = <&dps 0>;
225 flash@0 {
234 u-boot@0 {
235 reg = < 0 0x60000 >;
239 reg = < 0x60000 0x20000 >;
243 reg = < 0x80000 0x7F80000>;
258 u-boot@0 {
259 reg = < 0 0x60000 >;
263 reg = < 0x60000 0x20000 >;
267 reg = < 0x80000 0x7F80000>;
277 pinctrl-0 = <&pinctrl_spi1_default>;
279 flash@0 {
291 pinctrl-0 = <&pinctrl_txd1_default
305 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
321 pinctrl-0 = <&pinctrl_rmii1_default>;
342 reg = <0x52>;
344 #size-cells = <0>;
346 fan@0 {
348 reg = <0>;
409 reg = <0x60>;
411 #size-cells = <0>;
416 gpio@0 {
417 reg = <0>;
499 reg = <0x68>;
504 reg = <0x50>;
509 reg = <0x69>;
514 reg = <0x51>;
523 reg = <0x76>;
524 #io-channel-cells = <0>;
529 reg = <0x48>;
534 reg = <0x20>;
539 reg = <0x50>;
544 reg = <0x60>;
546 #size-cells = <0>;
551 gpio@0 {
552 reg = <0>;
598 reg = <0x60>;
600 #size-cells = <0>;
613 gpio@0 {
614 reg = <0>;
696 reg = <0x32>;
701 reg = <0x51>;
706 reg = <0x64>;
715 reg = <0x50>;
720 reg = <0x4c>;
725 reg = <0x71>;
730 reg = <0x72>;
735 reg = <0x74>;
737 #size-cells = <0>;
741 gpio@0 {
742 reg = <0>;
812 reg = <0x50>;
817 reg = <0x4c>;
822 reg = <0x71>;
827 reg = <0x72>;
832 reg = <0x74>;
834 #size-cells = <0>;
838 gpio@0 {
839 reg = <0>;
906 * -> PCIe Slot 0
919 reg = <0x48>;
924 reg = <0x4a>;
948 pinctrl-0 = <&pinctrl_wdtrst1_default>;
971 pinctrl-0 = <&pinctrl_sd2_default>;