Lines Matching +full:gic +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a5";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a5";
49 next-level-cache = <&L2>;
58 reserved-memory {
59 #address-cells = <1>;
60 #size-cells = <1>;
66 compatible = "shared-dma-pool";
68 no-map;
77 clock-names = "pxlclk";
80 memory-controller@2a150000 {
84 clock-names = "apb_pclk";
87 memory-controller@2a190000 {
93 clock-names = "apb_pclk";
97 compatible = "arm,cortex-a5-scu";
101 timer@2c000600 {
102 compatible = "arm,cortex-a5-twd-timer";
107 timer@2c000200 {
108 compatible = "arm,cortex-a5-global-timer",
109 "arm,cortex-a9-global-timer";
116 compatible = "arm,cortex-a5-twd-wdt";
121 gic: interrupt-controller@2c001000 { label
122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
123 #interrupt-cells = <3>;
124 #address-cells = <0>;
125 interrupt-controller;
130 L2: cache-controller@2c0f0000 {
131 compatible = "arm,pl310-cache";
134 cache-level = <2>;
135 cache-unified;
139 compatible = "arm,cortex-a5-pmu";
145 compatible = "arm,vexpress,config-bus";
146 arm,vexpress,config-bridge = <&v2m_sysreg>;
148 cpu_clk: clock-controller-0 {
150 compatible = "arm,vexpress-osc";
151 arm,vexpress-sysreg,func = <1 0>;
152 freq-range = <50000000 100000000>;
153 #clock-cells = <0>;
154 clock-output-names = "oscclk0";
157 axi_clk: clock-controller-1 {
159 compatible = "arm,vexpress-osc";
160 arm,vexpress-sysreg,func = <1 1>;
161 freq-range = <5000000 50000000>;
162 #clock-cells = <0>;
163 clock-output-names = "oscclk1";
166 clock-controller-2 {
168 compatible = "arm,vexpress-osc";
169 arm,vexpress-sysreg,func = <1 2>;
170 freq-range = <80000000 120000000>;
171 #clock-cells = <0>;
172 clock-output-names = "oscclk2";
175 hdlcd_clk: clock-controller-3 {
177 compatible = "arm,vexpress-osc";
178 arm,vexpress-sysreg,func = <1 3>;
179 freq-range = <23750000 165000000>;
180 #clock-cells = <0>;
181 clock-output-names = "oscclk3";
184 clock-controller-4 {
186 compatible = "arm,vexpress-osc";
187 arm,vexpress-sysreg,func = <1 4>;
188 freq-range = <80000000 80000000>;
189 #clock-cells = <0>;
190 clock-output-names = "oscclk4";
193 smbclk: clock-controller-5 {
195 compatible = "arm,vexpress-osc";
196 arm,vexpress-sysreg,func = <1 5>;
197 freq-range = <25000000 60000000>;
198 #clock-cells = <0>;
199 clock-output-names = "oscclk5";
202 temp-dcc {
204 compatible = "arm,vexpress-temp";
205 arm,vexpress-sysreg,func = <4 0>;
215 compatible = "simple-bus";
216 #address-cells = <1>;
217 #size-cells = <1>;
219 #interrupt-cells = <1>;
220 interrupt-map-mask = <0 3>;
221 interrupt-map = <0 0 &gic 0 36 4>,
222 <0 1 &gic 0 37 4>,
223 <0 2 &gic 0 38 4>,
224 <0 3 &gic 0 39 4>;