dts/arm/arm-realview-pb1176.dts

45 		/* 128 MiB memory @ 0x0 */
46 		reg = <0x00000000 0x08000000>;
67 		#clock-cells = <0>;
73 		#clock-cells = <0>;
82 		#clock-cells = <0>;
84 		clock-frequency = <0>;
89 		reg = <0x30000000 0x4000000>;
98 		reg = <0x38000000 0x800000>;
113 		reg = <0x3c000000 0x4000000>;
121 		reg = <0x3a000000 0x10000>;
123 		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
134 		reg = <0x3b000000 0x20000>;
136 		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
143 		#size-cells = <0>;
147 			#size-cells = <0>;
149 			port@0 {
150 				reg = <0>;
186 			reg = <0x10000000 0x1000>;
187 			ranges = <0x0 0x10000000 0x1000>;
191 			led@8,0 {
193 				reg = <0x08 0x04>;
194 				offset = <0x08>;
195 				mask = <0x01>;
196 				label = "versatile:0";
202 				reg = <0x08 0x04>;
203 				offset = <0x08>;
204 				mask = <0x02>;
211 				reg = <0x08 0x04>;
212 				offset = <0x08>;
213 				mask = <0x04>;
220 				reg = <0x08 0x04>;
221 				offset = <0x08>;
222 				mask = <0x08>;
228 				reg = <0x08 0x04>;
229 				offset = <0x08>;
230 				mask = <0x10>;
236 				reg = <0x08 0x04>;
237 				offset = <0x08>;
238 				mask = <0x20>;
244 				reg = <0x08 0x04>;
245 				offset = <0x08>;
246 				mask = <0x40>;
252 				reg = <0x08 0x04>;
253 				offset = <0x08>;
254 				mask = <0x80>;
260 				reg = <0x0c 0x04>;
261 				#clock-cells = <0>;
262 				lock-offset = <0x20>;
263 				vco-offset = <0x0C>;
268 				reg = <0x10 0x04>;
269 				#clock-cells = <0>;
270 				lock-offset = <0x20>;
271 				vco-offset = <0x10>;
276 				reg = <0x14 0x04>;
277 				#clock-cells = <0>;
278 				lock-offset = <0x20>;
279 				vco-offset = <0x14>;
284 				reg = <0x18 0x04>;
285 				#clock-cells = <0>;
286 				lock-offset = <0x20>;
287 				vco-offset = <0x18>;
292 				reg = <0x1c 0x04>;
293 				#clock-cells = <0>;
294 				lock-offset = <0x20>;
295 				vco-offset = <0x1c>;
306 			reg = <0x10121000 0x1000>,
307 			      <0x10120000 0x100>;
312 			reg = <0x10110000 0x1000>;
314 			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
331 			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
336 			reg = <0x10104000 0x1000>;
338 			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
345 			reg = <0x10105000 0x1000>;
347 			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
355 			reg = <0x10108000 0x1000>;
357 			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
364 			reg = <0x1010a000 0x1000>;
367 			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
377 			reg = <0x1010b000 0x1000>;
379 			interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
386 			reg = <0x1010c000 0x1000>;
388 			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
395 			reg = <0x1010d000 0x1000>;
397 			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
404 			reg = <0x1010e000 0x1000>;
406 			interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
413 			reg = <0x1010f000 0x1000>;
415 			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
423 			reg = <0x10200000 0x4000>;
429 			reg = <0x10112000 0x1000>;
432 			interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
441 					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
456 			#size-cells = <0>;
458 			reg = <0x10002000 0x1000>;
462 				reg = <0x68>;
468 			reg = <0x10004000 0x1000>;
470 			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
477 			reg = <0x10005000 0x1000>;
479 			interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
480 					<0 2 IRQ_TYPE_LEVEL_HIGH>;
489 			cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
495 			reg = <0x10006000 0x1000>;
497 			interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
504 			reg = <0x10007000 0x1000>;
506 			interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
513 			reg = <0x10008000 0x1000>;
515 			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
522 			reg = <0x10009000 0x1000>;
524 			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
535 			reg = <0x10041000 0x1000>,
536 			      <0x10040000 0x100>;
538 			interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
543 			reg = <0x10014000 0x1000>;
546 			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
556 			reg = <0x10015000 0x1000>;
559 			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
569 			reg = <0x10017000 0x1000>;
571 			interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;