Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ccu
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
62 #address-cells = <1>;
63 #size-cells = <1>;
66 simplefb_hdmi: framebuffer-lcd0-hdmi {
67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
77 simplefb_lcd: framebuffer-lcd0 {
78 compatible = "allwinner,simple-framebuffer",
79 "simple-framebuffer";
80 allwinner,pipeline = "de_be0-lcd0";
81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
89 compatible = "arm,armv7-timer";
94 clock-frequency = <24000000>;
95 arm,cpu-registers-not-fw-configured;
99 enable-method = "allwinner,sun6i-a31";
100 #address-cells = <1>;
101 #size-cells = <0>;
104 compatible = "arm,cortex-a7";
107 clocks = <&ccu CLK_CPU>;
108 clock-latency = <244144>; /* 8 32k periods */
109 operating-points =
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
122 clocks = <&ccu CLK_CPU>;
123 clock-latency = <244144>; /* 8 32k periods */
124 operating-points =
130 #cooling-cells = <2>;
134 compatible = "arm,cortex-a7";
137 clocks = <&ccu CLK_CPU>;
138 clock-latency = <244144>; /* 8 32k periods */
139 operating-points =
145 #cooling-cells = <2>;
149 compatible = "arm,cortex-a7";
152 clocks = <&ccu CLK_CPU>;
153 clock-latency = <244144>; /* 8 32k periods */
154 operating-points =
160 #cooling-cells = <2>;
164 thermal-zones {
165 cpu-thermal {
167 polling-delay-passive = <250>;
168 polling-delay = <1000>;
169 thermal-sensors = <&rtp>;
171 cooling-maps {
174 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
182 cpu_alert0: cpu-alert0 {
189 cpu_crit: cpu-crit {
200 compatible = "arm,cortex-a7-pmu";
208 #address-cells = <1>;
209 #size-cells = <1>;
212 osc24M: clk-24M {
213 #clock-cells = <0>;
214 compatible = "fixed-clock";
215 clock-frequency = <24000000>;
216 clock-accuracy = <50000>;
217 clock-output-names = "osc24M";
220 osc32k: clk-32k {
221 #clock-cells = <0>;
222 compatible = "fixed-clock";
223 clock-frequency = <32768>;
224 clock-accuracy = <50000>;
225 clock-output-names = "ext_osc32k";
232 * mode, using clk_set_rate auto-reparenting.
237 mii_phy_tx_clk: clk-mii-phy-tx {
238 #clock-cells = <0>;
239 compatible = "fixed-clock";
240 clock-frequency = <25000000>;
241 clock-output-names = "mii_phy_tx";
244 gmac_int_tx_clk: clk-gmac-int-tx {
245 #clock-cells = <0>;
246 compatible = "fixed-clock";
247 clock-frequency = <125000000>;
248 clock-output-names = "gmac_int_tx";
252 #clock-cells = <0>;
253 compatible = "allwinner,sun7i-a20-gmac-clk";
256 clock-output-names = "gmac_tx";
260 de: display-engine {
261 compatible = "allwinner,sun6i-a31-display-engine";
267 compatible = "simple-bus";
268 #address-cells = <1>;
269 #size-cells = <1>;
272 dma: dma-controller@1c02000 {
273 compatible = "allwinner,sun6i-a31-dma";
276 clocks = <&ccu CLK_AHB1_DMA>;
277 resets = <&ccu RST_AHB1_DMA>;
278 #dma-cells = <1>;
281 tcon0: lcd-controller@1c0c000 {
282 compatible = "allwinner,sun6i-a31-tcon";
286 resets = <&ccu RST_AHB1_LCD0>,
287 <&ccu RST_AHB1_LVDS>;
288 reset-names = "lcd",
290 clocks = <&ccu CLK_AHB1_LCD0>,
291 <&ccu CLK_LCD0_CH0>,
292 <&ccu CLK_LCD0_CH1>,
293 <&ccu 15>;
294 clock-names = "ahb",
295 "tcon-ch0",
296 "tcon-ch1",
297 "lvds-alt";
298 clock-output-names = "tcon0-pixel-clock";
299 #clock-cells = <0>;
302 #address-cells = <1>;
303 #size-cells = <0>;
306 #address-cells = <1>;
307 #size-cells = <0>;
312 remote-endpoint = <&drc0_out_tcon0>;
317 remote-endpoint = <&drc1_out_tcon0>;
322 #address-cells = <1>;
323 #size-cells = <0>;
328 remote-endpoint = <&hdmi_in_tcon0>;
329 allwinner,tcon-channel = <1>;
335 tcon1: lcd-controller@1c0d000 {
336 compatible = "allwinner,sun6i-a31-tcon";
340 resets = <&ccu RST_AHB1_LCD1>,
341 <&ccu RST_AHB1_LVDS>;
342 reset-names = "lcd", "lvds";
343 clocks = <&ccu CLK_AHB1_LCD1>,
344 <&ccu CLK_LCD1_CH0>,
345 <&ccu CLK_LCD1_CH1>,
346 <&ccu 15>;
347 clock-names = "ahb",
348 "tcon-ch0",
349 "tcon-ch1",
350 "lvds-alt";
351 clock-output-names = "tcon1-pixel-clock";
352 #clock-cells = <0>;
355 #address-cells = <1>;
356 #size-cells = <0>;
359 #address-cells = <1>;
360 #size-cells = <0>;
365 remote-endpoint = <&drc0_out_tcon1>;
370 remote-endpoint = <&drc1_out_tcon1>;
375 #address-cells = <1>;
376 #size-cells = <0>;
381 remote-endpoint = <&hdmi_in_tcon1>;
382 allwinner,tcon-channel = <1>;
389 compatible = "allwinner,sun7i-a20-mmc";
391 clocks = <&ccu CLK_AHB1_MMC0>,
392 <&ccu CLK_MMC0>,
393 <&ccu CLK_MMC0_OUTPUT>,
394 <&ccu CLK_MMC0_SAMPLE>;
395 clock-names = "ahb",
399 resets = <&ccu RST_AHB1_MMC0>;
400 reset-names = "ahb";
402 pinctrl-names = "default";
403 pinctrl-0 = <&mmc0_pins>;
405 #address-cells = <1>;
406 #size-cells = <0>;
410 compatible = "allwinner,sun7i-a20-mmc";
412 clocks = <&ccu CLK_AHB1_MMC1>,
413 <&ccu CLK_MMC1>,
414 <&ccu CLK_MMC1_OUTPUT>,
415 <&ccu CLK_MMC1_SAMPLE>;
416 clock-names = "ahb",
420 resets = <&ccu RST_AHB1_MMC1>;
421 reset-names = "ahb";
423 pinctrl-names = "default";
424 pinctrl-0 = <&mmc1_pins>;
426 #address-cells = <1>;
427 #size-cells = <0>;
431 compatible = "allwinner,sun7i-a20-mmc";
433 clocks = <&ccu CLK_AHB1_MMC2>,
434 <&ccu CLK_MMC2>,
435 <&ccu CLK_MMC2_OUTPUT>,
436 <&ccu CLK_MMC2_SAMPLE>;
437 clock-names = "ahb",
441 resets = <&ccu RST_AHB1_MMC2>;
442 reset-names = "ahb";
445 #address-cells = <1>;
446 #size-cells = <0>;
450 compatible = "allwinner,sun7i-a20-mmc";
452 clocks = <&ccu CLK_AHB1_MMC3>,
453 <&ccu CLK_MMC3>,
454 <&ccu CLK_MMC3_OUTPUT>,
455 <&ccu CLK_MMC3_SAMPLE>;
456 clock-names = "ahb",
460 resets = <&ccu RST_AHB1_MMC3>;
461 reset-names = "ahb";
464 #address-cells = <1>;
465 #size-cells = <0>;
469 compatible = "allwinner,sun6i-a31-hdmi";
472 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
473 <&ccu CLK_HDMI_DDC>,
474 <&ccu CLK_PLL_VIDEO0_2X>,
475 <&ccu CLK_PLL_VIDEO1_2X>;
476 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
477 resets = <&ccu RST_AHB1_HDMI>;
478 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
483 #address-cells = <1>;
484 #size-cells = <0>;
487 #address-cells = <1>;
488 #size-cells = <0>;
493 remote-endpoint = <&tcon0_out_hdmi>;
498 remote-endpoint = <&tcon1_out_hdmi>;
509 compatible = "allwinner,sun6i-a31-musb";
511 clocks = <&ccu CLK_AHB1_OTG>;
512 resets = <&ccu RST_AHB1_OTG>;
514 interrupt-names = "mc";
516 phy-names = "usb";
523 compatible = "allwinner,sun6i-a31-usb-phy";
527 reg-names = "phy_ctrl",
530 clocks = <&ccu CLK_USB_PHY0>,
531 <&ccu CLK_USB_PHY1>,
532 <&ccu CLK_USB_PHY2>;
533 clock-names = "usb0_phy",
536 resets = <&ccu RST_USB_PHY0>,
537 <&ccu RST_USB_PHY1>,
538 <&ccu RST_USB_PHY2>;
539 reset-names = "usb0_reset",
543 #phy-cells = <1>;
547 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
550 clocks = <&ccu CLK_AHB1_EHCI0>;
551 resets = <&ccu RST_AHB1_EHCI0>;
553 phy-names = "usb";
558 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
561 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
562 resets = <&ccu RST_AHB1_OHCI0>;
564 phy-names = "usb";
569 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
572 clocks = <&ccu CLK_AHB1_EHCI1>;
573 resets = <&ccu RST_AHB1_EHCI1>;
575 phy-names = "usb";
580 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
583 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
584 resets = <&ccu RST_AHB1_OHCI1>;
586 phy-names = "usb";
591 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
594 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
595 resets = <&ccu RST_AHB1_OHCI2>;
599 ccu: clock@1c20000 { label
600 compatible = "allwinner,sun6i-a31-ccu";
603 clock-names = "hosc", "losc";
604 #clock-cells = <1>;
605 #reset-cells = <1>;
609 compatible = "allwinner,sun6i-a31-pinctrl";
611 interrupt-parent = <&r_intc>;
616 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
618 clock-names = "apb", "hosc", "losc";
619 gpio-controller;
620 interrupt-controller;
621 #interrupt-cells = <3>;
622 #gpio-cells = <3>;
624 gmac_gmii_pins: gmac-gmii-pins {
637 drive-strength = <30>;
640 gmac_mii_pins: gmac-mii-pins {
649 gmac_rgmii_pins: gmac-rgmii-pins {
659 drive-strength = <40>;
662 i2c0_pins: i2c0-pins {
667 i2c1_pins: i2c1-pins {
672 i2c2_pins: i2c2-pins {
677 lcd0_rgb888_pins: lcd0-rgb888-pins {
688 mmc0_pins: mmc0-pins {
692 drive-strength = <30>;
693 bias-pull-up;
696 mmc1_pins: mmc1-pins {
700 drive-strength = <30>;
701 bias-pull-up;
704 mmc2_4bit_pins: mmc2-4bit-pins {
708 drive-strength = <30>;
709 bias-pull-up;
712 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
718 drive-strength = <30>;
719 bias-pull-up;
722 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
728 drive-strength = <40>;
729 bias-pull-up;
732 spdif_tx_pin: spdif-tx-pin {
737 uart0_ph_pins: uart0-ph-pins {
744 compatible = "allwinner,sun4i-a10-timer";
756 compatible = "allwinner,sun6i-a31-wdt";
763 #sound-dai-cells = <0>;
764 compatible = "allwinner,sun6i-a31-spdif";
767 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
768 resets = <&ccu RST_APB1_SPDIF>;
769 clock-names = "apb", "spdif";
771 dma-names = "rx", "tx";
776 #sound-dai-cells = <0>;
777 compatible = "allwinner,sun6i-a31-i2s";
780 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
781 resets = <&ccu RST_APB1_DAUDIO0>;
782 clock-names = "apb", "mod";
784 dma-names = "rx", "tx";
789 #sound-dai-cells = <0>;
790 compatible = "allwinner,sun6i-a31-i2s";
793 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
794 resets = <&ccu RST_APB1_DAUDIO1>;
795 clock-names = "apb", "mod";
797 dma-names = "rx", "tx";
802 compatible = "allwinner,sun4i-a10-lradc-keys";
804 interrupt-parent = <&r_intc>;
810 compatible = "allwinner,sun6i-a31-ts";
813 #thermal-sensor-cells = <0>;
817 compatible = "snps,dw-apb-uart";
820 reg-shift = <2>;
821 reg-io-width = <4>;
822 clocks = <&ccu CLK_APB2_UART0>;
823 resets = <&ccu RST_APB2_UART0>;
825 dma-names = "tx", "rx";
830 compatible = "snps,dw-apb-uart";
833 reg-shift = <2>;
834 reg-io-width = <4>;
835 clocks = <&ccu CLK_APB2_UART1>;
836 resets = <&ccu RST_APB2_UART1>;
838 dma-names = "tx", "rx";
843 compatible = "snps,dw-apb-uart";
846 reg-shift = <2>;
847 reg-io-width = <4>;
848 clocks = <&ccu CLK_APB2_UART2>;
849 resets = <&ccu RST_APB2_UART2>;
851 dma-names = "tx", "rx";
856 compatible = "snps,dw-apb-uart";
859 reg-shift = <2>;
860 reg-io-width = <4>;
861 clocks = <&ccu CLK_APB2_UART3>;
862 resets = <&ccu RST_APB2_UART3>;
864 dma-names = "tx", "rx";
869 compatible = "snps,dw-apb-uart";
872 reg-shift = <2>;
873 reg-io-width = <4>;
874 clocks = <&ccu CLK_APB2_UART4>;
875 resets = <&ccu RST_APB2_UART4>;
877 dma-names = "tx", "rx";
882 compatible = "snps,dw-apb-uart";
885 reg-shift = <2>;
886 reg-io-width = <4>;
887 clocks = <&ccu CLK_APB2_UART5>;
888 resets = <&ccu RST_APB2_UART5>;
890 dma-names = "tx", "rx";
895 compatible = "allwinner,sun6i-a31-i2c";
898 clocks = <&ccu CLK_APB2_I2C0>;
899 resets = <&ccu RST_APB2_I2C0>;
900 pinctrl-names = "default";
901 pinctrl-0 = <&i2c0_pins>;
903 #address-cells = <1>;
904 #size-cells = <0>;
908 compatible = "allwinner,sun6i-a31-i2c";
911 clocks = <&ccu CLK_APB2_I2C1>;
912 resets = <&ccu RST_APB2_I2C1>;
913 pinctrl-names = "default";
914 pinctrl-0 = <&i2c1_pins>;
916 #address-cells = <1>;
917 #size-cells = <0>;
921 compatible = "allwinner,sun6i-a31-i2c";
924 clocks = <&ccu CLK_APB2_I2C2>;
925 resets = <&ccu RST_APB2_I2C2>;
926 pinctrl-names = "default";
927 pinctrl-0 = <&i2c2_pins>;
929 #address-cells = <1>;
930 #size-cells = <0>;
934 compatible = "allwinner,sun6i-a31-i2c";
937 clocks = <&ccu CLK_APB2_I2C3>;
938 resets = <&ccu RST_APB2_I2C3>;
940 #address-cells = <1>;
941 #size-cells = <0>;
945 compatible = "allwinner,sun7i-a20-gmac";
948 interrupt-names = "macirq";
949 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
950 clock-names = "stmmaceth", "allwinner_gmac_tx";
951 resets = <&ccu RST_AHB1_EMAC>;
952 reset-names = "stmmaceth";
954 snps,fixed-burst;
959 compatible = "snps,dwmac-mdio";
960 #address-cells = <1>;
961 #size-cells = <0>;
965 crypto: crypto-engine@1c15000 {
966 compatible = "allwinner,sun6i-a31-crypto",
967 "allwinner,sun4i-a10-crypto";
970 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
971 clock-names = "ahb", "mod";
972 resets = <&ccu RST_AHB1_SS>;
973 reset-names = "ahb";
977 #sound-dai-cells = <0>;
978 compatible = "allwinner,sun6i-a31-codec";
981 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
982 clock-names = "apb", "codec";
983 resets = <&ccu RST_APB1_CODEC>;
985 dma-names = "rx", "tx";
990 compatible = "allwinner,sun6i-a31-hstimer",
991 "allwinner,sun7i-a20-hstimer";
997 clocks = <&ccu CLK_AHB1_HSTIMER>;
998 resets = <&ccu RST_AHB1_HSTIMER>;
1002 compatible = "allwinner,sun6i-a31-spi";
1005 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
1006 clock-names = "ahb", "mod";
1008 dma-names = "rx", "tx";
1009 resets = <&ccu RST_AHB1_SPI0>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 compatible = "allwinner,sun6i-a31-spi";
1019 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1020 clock-names = "ahb", "mod";
1022 dma-names = "rx", "tx";
1023 resets = <&ccu RST_AHB1_SPI1>;
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1030 compatible = "allwinner,sun6i-a31-spi";
1033 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1034 clock-names = "ahb", "mod";
1036 dma-names = "rx", "tx";
1037 resets = <&ccu RST_AHB1_SPI2>;
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1044 compatible = "allwinner,sun6i-a31-spi";
1047 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1048 clock-names = "ahb", "mod";
1050 dma-names = "rx", "tx";
1051 resets = <&ccu RST_AHB1_SPI3>;
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1057 gic: interrupt-controller@1c81000 {
1058 compatible = "arm,gic-400";
1063 interrupt-controller;
1064 #interrupt-cells = <3>;
1068 fe0: display-frontend@1e00000 {
1069 compatible = "allwinner,sun6i-a31-display-frontend";
1072 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1073 <&ccu CLK_DRAM_FE0>;
1074 clock-names = "ahb", "mod",
1076 resets = <&ccu RST_AHB1_FE0>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1089 remote-endpoint = <&be0_in_fe0>;
1094 remote-endpoint = <&be1_in_fe0>;
1100 fe1: display-frontend@1e20000 {
1101 compatible = "allwinner,sun6i-a31-display-frontend";
1104 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1105 <&ccu CLK_DRAM_FE1>;
1106 clock-names = "ahb", "mod",
1108 resets = <&ccu RST_AHB1_FE1>;
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1121 remote-endpoint = <&be0_in_fe1>;
1126 remote-endpoint = <&be1_in_fe1>;
1132 be1: display-backend@1e40000 {
1133 compatible = "allwinner,sun6i-a31-display-backend";
1136 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1137 <&ccu CLK_DRAM_BE1>;
1138 clock-names = "ahb", "mod",
1140 resets = <&ccu RST_AHB1_BE1>;
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1153 remote-endpoint = <&fe0_out_be1>;
1158 remote-endpoint = <&fe1_out_be1>;
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1169 remote-endpoint = <&drc1_in_be1>;
1176 compatible = "allwinner,sun6i-a31-drc";
1179 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1180 <&ccu CLK_DRAM_DRC1>;
1181 clock-names = "ahb", "mod",
1183 resets = <&ccu RST_AHB1_DRC1>;
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1196 remote-endpoint = <&be1_out_drc1>;
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1207 remote-endpoint = <&tcon0_in_drc1>;
1212 remote-endpoint = <&tcon1_in_drc1>;
1218 be0: display-backend@1e60000 {
1219 compatible = "allwinner,sun6i-a31-display-backend";
1222 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1223 <&ccu CLK_DRAM_BE0>;
1224 clock-names = "ahb", "mod",
1226 resets = <&ccu RST_AHB1_BE0>;
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1239 remote-endpoint = <&fe0_out_be0>;
1244 remote-endpoint = <&fe1_out_be0>;
1252 remote-endpoint = <&drc0_in_be0>;
1259 compatible = "allwinner,sun6i-a31-drc";
1262 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1263 <&ccu CLK_DRAM_DRC0>;
1264 clock-names = "ahb", "mod",
1266 resets = <&ccu RST_AHB1_DRC0>;
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1276 remote-endpoint = <&be0_out_drc0>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1287 remote-endpoint = <&tcon0_in_drc0>;
1292 remote-endpoint = <&tcon1_in_drc0>;
1299 #clock-cells = <1>;
1300 compatible = "allwinner,sun6i-a31-rtc";
1302 interrupt-parent = <&r_intc>;
1306 clock-output-names = "osc32k";
1309 r_intc: interrupt-controller@1f00c00 {
1310 compatible = "allwinner,sun6i-a31-r-intc";
1311 interrupt-controller;
1312 #interrupt-cells = <3>;
1318 compatible = "allwinner,sun6i-a31-prcm";
1321 ar100: ar100-clk {
1322 compatible = "allwinner,sun6i-a31-ar100-clk";
1323 #clock-cells = <0>;
1325 <&ccu CLK_PLL_PERIPH>,
1326 <&ccu CLK_PLL_PERIPH>;
1327 clock-output-names = "ar100";
1330 ahb0: ahb0-clk {
1331 compatible = "fixed-factor-clock";
1332 #clock-cells = <0>;
1333 clock-div = <1>;
1334 clock-mult = <1>;
1336 clock-output-names = "ahb0";
1339 apb0: apb0-clk {
1340 compatible = "allwinner,sun6i-a31-apb0-clk";
1341 #clock-cells = <0>;
1343 clock-output-names = "apb0";
1346 apb0_gates: apb0-gates-clk {
1347 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1348 #clock-cells = <1>;
1350 clock-output-names = "apb0_pio", "apb0_ir",
1356 ir_clk: ir-clk {
1357 #clock-cells = <0>;
1358 compatible = "allwinner,sun4i-a10-mod0-clk";
1360 clock-output-names = "ir";
1363 apb0_rst: apb0-rst {
1364 compatible = "allwinner,sun6i-a31-clock-reset";
1365 #reset-cells = <1>;
1370 compatible = "allwinner,sun6i-a31-cpuconfig";
1375 compatible = "allwinner,sun6i-a31-ir";
1377 clock-names = "apb", "ir";
1385 compatible = "allwinner,sun6i-a31-r-pinctrl";
1387 interrupt-parent = <&r_intc>;
1391 clock-names = "apb", "hosc", "losc";
1392 gpio-controller;
1393 interrupt-controller;
1394 #interrupt-cells = <3>;
1395 #gpio-cells = <3>;
1397 s_ir_rx_pin: s-ir-rx-pin {
1402 s_p2wi_pins: s-p2wi-pins {
1409 compatible = "allwinner,sun6i-a31-p2wi";
1413 clock-frequency = <100000>;
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&s_p2wi_pins>;
1418 #address-cells = <1>;
1419 #size-cells = <0>;