Lines Matching full:r0
81 mov r0, \val
86 mov r0, \val
241 mov r0, #0x17 @ angel_SWIreason_EnterSVC
245 safe_svcmode_maskall r0
279 mov r0, pc
280 and r0, r0, #0xf8000000
312 add r4, r0, #TEXT_OFFSET
323 mov r0, pc
324 cmp r0, r4
325 ldrcc r0, .Lheadroom
326 addcc r0, r0, pc
327 cmpcc r4, r0
331 restart: adr r0, LC1
332 ldr sp, [r0]
333 ldr r6, [r0, #4]
334 add sp, sp, r0
335 add r6, r6, r0
399 mov r0, r8
409 cmp r0, #1
410 sub r0, r4, #TEXT_OFFSET
411 bic r0, r0, #1
412 add r0, r0, #0x100
488 mrs r0, spsr
489 and r0, r0, #MODE_MASK
490 cmp r0, #HYP_MODE
498 adr_l r0, __hyp_stub_vectors
499 sub r0, r0, r5
500 add r0, r0, r10
525 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
527 stmdb r9!, {r0 - r3, r10 - r12, lr}
533 mov r0, r9 @ start of relocated zImage
537 badr r0, restart
538 add r0, r0, r6
539 mov pc, r0
542 adr r0, LC0
543 ldmia r0, {r1, r2, r3, r11, r12}
544 sub r0, r0, r1 @ calculate the delta offset
548 * r0 = delta
559 orrs r1, r0, r5
562 add r11, r11, r0
563 add r12, r12, r0
571 add r2, r2, r0
572 add r3, r3, r0
579 add r1, r1, r0 @ This fixes up C references
600 addlo r1, r1, r0 @ table. This fixes up the
606 not_relocated: mov r0, #0
607 1: str r0, [r2], #4 @ clear bss
608 str r0, [r2], #4
609 str r0, [r2], #4
610 str r0, [r2], #4
630 mov r0, r4
638 mov r0, r4 @ start of inflated image
639 add r1, r1, r0 @ end of inflated image
644 mrs r0, spsr @ Get saved CPU boot mode
645 and r0, r0, #MODE_MASK
646 cmp r0, #HYP_MODE @ if not booted in HYP mode...
649 adr_l r0, __hyp_reentry_vectors
680 params: ldr r0, =0x10000100 @ params_phys for RPC
717 * r0, r1, r2, r3, r9, r10, r12 corrupted
730 mov r0, #0x3f @ 4G, the whole
731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
732 mcr p15, 0, r0, c6, c7, 1
734 mov r0, #0x80 @ PR7
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
739 mov r0, #0xc000
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
743 mov r0, #0
744 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
746 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
747 mrc p15, 0, r0, c1, c0, 0 @ read control reg
749 orr r0, r0, #0x002d @ .... .... ..1. 11.1
750 orr r0, r0, #0x1000 @ ...1 .... .... ....
752 mcr p15, 0, r0, c1, c0, 0 @ write control reg
754 mov r0, #0
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
756 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
760 mov r0, #0x3f @ 4G, the whole
761 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
763 mov r0, #0x80 @ PR7
764 mcr p15, 0, r0, c2, c0, 0 @ cache on
765 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
767 mov r0, #0xc000
768 mcr p15, 0, r0, c5, c0, 0 @ access permission
770 mov r0, #0
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
776 mrc p15, 0, r0, c1, c0, 0 @ read control reg
778 orr r0, r0, #0x000d @ .... .... .... 11.1
780 mov r0, #0
781 mcr p15, 0, r0, c1, c0, 0 @ write control reg
784 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
800 mov r0, r3
801 mov r9, r0, lsr #18
812 str r1, [r0], #4 @ 1:1 mapping
814 teq r0, r2
827 add r0, r3, r2, lsl #2
828 str r1, [r0], #4
830 str r1, [r0]
837 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
838 bic r0, r0, #2 @ A (no unaligned access fault)
839 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
840 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
845 mov r0, #4 @ put dcache in WT mode
846 mcr p15, 7, r0, c15, c0, 0
854 mov r0, #0
855 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
856 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
857 mrc p15, 0, r0, c1, c0, 0 @ read control reg
858 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
859 orr r0, r0, #0x0030
860 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
862 mov r0, #0
863 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
875 mov r0, #0
876 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
878 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
880 mrc p15, 0, r0, c1, c0, 0 @ read control reg
881 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
882 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
883 orr r0, r0, #0x003c @ write buffer
884 bic r0, r0, #2 @ A (no unaligned access fault)
885 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
888 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
890 orrne r0, r0, #1 @ MMU enabled
898 mcr p15, 0, r0, c7, c5, 4 @ ISB
899 mcr p15, 0, r0, c1, c0, 0 @ load control register
900 mrc p15, 0, r0, c1, c0, 0 @ and read it back
901 mov r0, #0
902 mcr p15, 0, r0, c7, c5, 4 @ ISB
909 mov r0, #0
910 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
911 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
912 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
913 mrc p15, 0, r0, c1, c0, 0 @ read control reg
914 orr r0, r0, #0x1000 @ I-cache enable
916 mov r0, #0
917 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
923 orr r0, r0, #0x000d @ Write buffer, mmu
930 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
931 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
932 sub pc, lr, r0, lsr #32 @ properly flush pipeline
1151 * r0, r1, r2, r3, r9, r12 corrupted
1160 mrc p15, 0, r0, c1, c0
1161 bic r0, r0, #0x000d
1162 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1163 mov r0, #0
1164 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1165 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1166 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1170 mrc p15, 0, r0, c1, c0
1171 bic r0, r0, #0x000d
1172 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1173 mov r0, #0
1174 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1179 mrc p15, 0, r0, c1, c0
1180 bic r0, r0, #0x000d
1181 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1182 mov r0, #0
1183 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1184 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1189 mrc p15, 0, r0, c1, c0
1191 bic r0, r0, #0x0005
1193 bic r0, r0, #0x0004
1195 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1196 mov r0, #0
1198 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1200 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1201 mcr p15, 0, r0, c7, c10, 4 @ DSB
1202 mcr p15, 0, r0, c7, c5, 4 @ ISB
1209 * r0 = start address
1272 bic r0, r0, r2 @ round down start to line size
1275 0: cmp r0, r11 @ finished?
1277 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1278 add r0, r0, r1
1292 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1293 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1348 @ phex corrupts {r0, r1, r2, r3}
1353 movmi r0, r3
1355 and r2, r0, #15
1356 mov r0, r0, lsr #4
1363 @ puts corrupts {r0, r1, r2, r3}
1365 1: ldrb r2, [r0], #1
1375 teq r0, #0
1378 @ putc corrupts {r0, r1, r2, r3}
1380 mov r2, r0
1381 loadsp r3, r1, r0
1382 mov r0, #0
1385 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1386 memdump: mov r12, r0
1389 2: mov r0, r11, lsl #2
1390 add r0, r0, r12
1393 mov r0, #':'
1395 1: mov r0, #' '
1397 ldr r0, [r12, r11, lsl #2]
1400 and r0, r11, #7
1401 teq r0, #3
1402 moveq r0, #' '
1404 and r0, r11, #7
1406 teq r0, #7
1408 mov r0, #'\n'
1435 mov r0, #0 @ must be 0
1446 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1447 bic r0, r0, #0x5 @ disable MMU and caches
1448 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1453 mov r4, r0 @ preserve image base
1456 adr_l r0, call_cache_fn
1470 mrs r0, cpsr @ get the current mode
1471 msr spsr_cxsf, r0 @ record boot mode
1472 and r0, r0, #MODE_MASK @ are we running in HYP mode?
1473 cmp r0, #HYP_MODE
1490 adr r0, __hyp_reentry_vectors
1491 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1503 msr spsr_cxsf, r0 @ record boot mode
1508 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1509 tst r0, #0x1 @ MMU enabled?
1513 mov r0, r8 @ DT start
1517 adr r0, 0f @ switch to our stack
1518 ldr sp, [r0]
1519 add sp, sp, r0