Lines Matching +full:2 +full:c0
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
164 ldrb \tmp2, [\tmp1, #2]
658 .align 2
696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
747 mrc p15, 0, r0, c1, c0, 0 @ read control reg
752 mcr p15, 0, r0, c1, c0, 0 @ write control reg
764 mcr p15, 0, r0, c2, c0, 0 @ cache on
765 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
768 mcr p15, 0, r0, c5, c0, 0 @ access permission
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
776 mrc p15, 0, r0, c1, c0, 0 @ read control reg
781 mcr p15, 0, r0, c1, c0, 0 @ write control reg
784 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
818 * to be enabled also for our execution instance... We map 2MB of it
827 add r0, r3, r2, lsl #2
837 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
838 bic r0, r0, #2 @ A (no unaligned access fault)
840 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
846 mcr p15, 7, r0, c15, c0, 0
857 mrc p15, 0, r0, c1, c0, 0 @ read control reg
871 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
880 mrc p15, 0, r0, c1, c0, 0 @ read control reg
884 bic r0, r0, #2 @ A (no unaligned access fault)
889 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
894 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
895 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
896 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
899 mcr p15, 0, r0, c1, c0, 0 @ load control register
900 mrc p15, 0, r0, c1, c0, 0 @ and read it back
913 mrc p15, 0, r0, c1, c0, 0 @ read control reg
926 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
927 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
930 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
931 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
953 mrc p15, 0, r9, c0, c0 @ get processor ID
991 .align 2
1160 mrc p15, 0, r0, c1, c0
1162 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1170 mrc p15, 0, r0, c1, c0
1172 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1174 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1179 mrc p15, 0, r0, c1, c0
1181 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1189 mrc p15, 0, r0, c1, c0
1195 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1230 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1232 bcs 2b @ entries 63 to 0
1263 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1299 mov r2, #64*1024 @ default: 32K dcache size (*2)
1301 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1307 mov r2, r2, lsl r1 @ base dcache size *2
1309 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1335 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1343 .align 2
1368 2: writeb r2, r3, r1
1374 beq 2b
1383 b 2b
1389 2: mov r0, r11, lsl #2
1397 ldr r0, [r12, r11, lsl #2]
1411 blt 2b
1446 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1448 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1476 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1489 mcr p15, 4, r1, c1, c0, 0
1491 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1508 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR