Lines Matching +full:1 +full:c0
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
142 tst \reg, #(1 << 5) @ CP15BEN bit set?
144 orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions
145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
162 ldrb \tmp2, [\tmp1, #1]
191 * These 7 nops along with the 1 nop immediately below for
213 W(b) 1f
223 1:
295 beq 1f @ if yes, skip validation
309 1:
321 * additional 1MB of room for a possible appended DTB.
328 orrcc r4, r4, #1 @ remember we skipped cache_on
387 add r5, r5, r5, lsr #1
391 /* clamp to 32KB min and 1MB max */
392 cmp r5, #(1 << 15)
393 movlo r5, #(1 << 15)
394 cmp r5, #(1 << 20)
395 movhi r5, #(1 << 20)
405 * If returned value is 1, there is no ATAG at the location
409 cmp r0, #1
411 bic r0, r0, #1
491 bne 1f
502 1:
525 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
528 bhi 1b
578 1: ldr r1, [r11, #0] @ relocate entries in the GOT
585 blo 1b
597 1: ldr r1, [r11, #0] @ relocate entries in the GOT
603 blo 1b
607 1: str r0, [r2], #4 @ clear bss
612 blo 1b
619 tst r4, #1
620 bic r4, r4, #1
696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
732 mcr p15, 0, r0, c6, c7, 1
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
747 mrc p15, 0, r0, c1, c0, 0 @ read control reg
749 orr r0, r0, #0x002d @ .... .... ..1. 11.1
750 orr r0, r0, #0x1000 @ ...1 .... .... ....
752 mcr p15, 0, r0, c1, c0, 0 @ write control reg
764 mcr p15, 0, r0, c2, c0, 0 @ cache on
765 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
768 mcr p15, 0, r0, c5, c0, 0 @ access permission
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
776 mrc p15, 0, r0, c1, c0, 0 @ read control reg
781 mcr p15, 0, r0, c1, c0, 0 @ write control reg
784 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
807 1: cmp r1, r9 @ if virt > start of RAM
812 str r1, [r0], #4 @ 1:1 mapping
815 bne 1b
819 * so there is no map overlap problem for up to 1 MB compressed kernel.
837 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
839 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
840 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
846 mcr p15, 7, r0, c15, c0, 0
857 mrc p15, 0, r0, c1, c0, 0 @ read control reg
860 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
871 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
880 mrc p15, 0, r0, c1, c0, 0 @ read control reg
881 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
885 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
888 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
889 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
890 orrne r0, r0, #1 @ MMU enabled
892 bic r6, r6, #1 << 31 @ 32-bit translation system
893 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
894 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
895 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
896 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
899 mcr p15, 0, r0, c1, c0, 0 @ load control register
900 mrc p15, 0, r0, c1, c0, 0 @ and read it back
913 mrc p15, 0, r0, c1, c0, 0 @ read control reg
925 mov r1, #-1
926 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
927 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
928 b 1f
930 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
931 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
953 mrc p15, 0, r9, c0, c0 @ get processor ID
967 1: ldr r1, [r12, #0] @ get value
975 b 1b
1160 mrc p15, 0, r0, c1, c0
1162 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1170 mrc p15, 0, r0, c1, c0
1172 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1174 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1179 mrc p15, 0, r0, c1, c0
1181 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1189 mrc p15, 0, r0, c1, c0
1195 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1223 tst r4, #1
1225 mov r2, #1
1229 1: orr r3, r1, #63 << 26 @ 64 entries
1231 subs r3, r3, #1 << 26
1233 subs r1, r1, #1 << 5
1234 bcs 1b @ segments 7 to 0
1242 tst r4, #1
1252 tst r4, #1
1261 tst r4, #1
1263 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1271 sub r2, r1, #1 @ r2 := line size mask
1273 sub r11, r11, #1 @ end address is exclusive
1277 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1288 tst r4, #1
1290 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1291 bne 1b
1297 tst r4, #1
1301 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1308 tst r3, #1 << 14 @ test M bit
1309 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1318 1:
1323 bne 1b
1332 tst r4, #1
1335 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1352 1: subs r1, r1, #1
1361 b 1b
1365 1: ldrb r2, [r0], #1
1370 3: subs r1, r1, #1
1376 bne 1b
1395 1: mov r0, #' '
1405 add r11, r11, #1
1407 bne 1b
1439 M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
1446 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1448 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1464 @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1476 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1478 beq 1f
1482 @ off just carrying on using the cached 1:1 mapping that the
1487 ARM( bic r1, r1, #(1 << 30) ) @ clear HSCTLR.TE
1488 THUMB( orr r1, r1, #(1 << 30) ) @ set HSCTLR.TE
1489 mcr p15, 4, r1, c1, c0, 0
1491 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1498 @ 1:1 mapping as usual.
1500 1: mov r9, r4 @ preserve image base
1504 orr r4, r9, #1 @ restore image base and set LSB
1508 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1510 orreq r4, r4, #1 @ set LSB if not