Lines Matching +full:cortex +full:- +full:a
1 # SPDX-License-Identifier: GPL-2.0
159 The ARM series is a line of low-power-consumption RISC chip designs
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
163 Europe. There is an ARM Linux project with a web page at
172 relocations, which have been around for a long time, but were not
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
190 size. This works well for buffers up to a few hundreds kilobytes, but
191 for larger buffers it just a waste of address space. Drivers which has
193 virtual space with just a few allocations.
197 specified order. The order is expressed as a power of two multiplied
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
271 of physical memory is at a 2 MiB boundary.
274 this feature (eg, building a kernel for a single machine) and
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
341 In general, all Arm machines can be supported in a single
354 # This is sorted alphabetically by mach-* pathname. However, plat-*
356 # plat- suffix) or along side the corresponding mach-* source.
358 source "arch/arm/mach-actions/Kconfig"
360 source "arch/arm/mach-alpine/Kconfig"
362 source "arch/arm/mach-artpec/Kconfig"
364 source "arch/arm/mach-aspeed/Kconfig"
366 source "arch/arm/mach-at91/Kconfig"
368 source "arch/arm/mach-axxia/Kconfig"
370 source "arch/arm/mach-bcm/Kconfig"
372 source "arch/arm/mach-berlin/Kconfig"
374 source "arch/arm/mach-clps711x/Kconfig"
376 source "arch/arm/mach-davinci/Kconfig"
378 source "arch/arm/mach-digicolor/Kconfig"
380 source "arch/arm/mach-dove/Kconfig"
382 source "arch/arm/mach-ep93xx/Kconfig"
384 source "arch/arm/mach-exynos/Kconfig"
386 source "arch/arm/mach-footbridge/Kconfig"
388 source "arch/arm/mach-gemini/Kconfig"
390 source "arch/arm/mach-highbank/Kconfig"
392 source "arch/arm/mach-hisi/Kconfig"
394 source "arch/arm/mach-hpe/Kconfig"
396 source "arch/arm/mach-imx/Kconfig"
398 source "arch/arm/mach-ixp4xx/Kconfig"
400 source "arch/arm/mach-keystone/Kconfig"
402 source "arch/arm/mach-lpc32xx/Kconfig"
404 source "arch/arm/mach-mediatek/Kconfig"
406 source "arch/arm/mach-meson/Kconfig"
408 source "arch/arm/mach-milbeaut/Kconfig"
410 source "arch/arm/mach-mmp/Kconfig"
412 source "arch/arm/mach-mstar/Kconfig"
414 source "arch/arm/mach-mv78xx0/Kconfig"
416 source "arch/arm/mach-mvebu/Kconfig"
418 source "arch/arm/mach-mxs/Kconfig"
420 source "arch/arm/mach-nomadik/Kconfig"
422 source "arch/arm/mach-npcm/Kconfig"
424 source "arch/arm/mach-omap1/Kconfig"
426 source "arch/arm/mach-omap2/Kconfig"
428 source "arch/arm/mach-orion5x/Kconfig"
430 source "arch/arm/mach-pxa/Kconfig"
432 source "arch/arm/mach-qcom/Kconfig"
434 source "arch/arm/mach-realtek/Kconfig"
436 source "arch/arm/mach-rpc/Kconfig"
438 source "arch/arm/mach-rockchip/Kconfig"
440 source "arch/arm/mach-s3c/Kconfig"
442 source "arch/arm/mach-s5pv210/Kconfig"
444 source "arch/arm/mach-sa1100/Kconfig"
446 source "arch/arm/mach-shmobile/Kconfig"
448 source "arch/arm/mach-socfpga/Kconfig"
450 source "arch/arm/mach-spear/Kconfig"
452 source "arch/arm/mach-sti/Kconfig"
454 source "arch/arm/mach-stm32/Kconfig"
456 source "arch/arm/mach-sunxi/Kconfig"
458 source "arch/arm/mach-tegra/Kconfig"
460 source "arch/arm/mach-ux500/Kconfig"
462 source "arch/arm/mach-versatile/Kconfig"
464 source "arch/arm/mach-vt8500/Kconfig"
466 source "arch/arm/mach-zynq/Kconfig"
468 # ARMv7-M architecture
477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
487 with a range of available cores like Cortex-M3/M4/M7.
517 running on a CPU that supports it.
520 source "arch/arm/Kconfig-nommu"
528 When coming out of either a Wait for Interrupt (WFI) or a Wait for
529 Event (WFE) IDLE states, a specific timing sensitivity exists between
531 instructions. This sensitivity can result in a CPU hang scenario.
533 The software must insert either a Data Synchronization Barrier (DSB)
538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
541 Executing a SWP instruction to read-only memory does not set bit 11
543 treat the access as a read, preventing a COW from occurring and
559 This option enables the workaround for the 430973 Cortex-A8
560 r1p* erratum. If a code sequence containing an ARM/Thumb
562 same virtual address, whether due to self-modifying code or virtual
563 to physical address re-mapping, Cortex-A8 does not recover from the
564 stale interworking branch prediction. This results in Cortex-A8
569 available in non-secure mode.
572 bool "ARM errata: Processor deadlock when a false hazard is created"
576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
578 possible for a hazard condition intended for a cache line to instead
579 be incorrectly associated with a different cache line. This false
580 hazard might then cause a processor deadlock. The workaround enables
583 register may not be available in non-secure mode and thus is not
584 available on a multiplatform kernel. This should be applied by the
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
593 erratum. Any asynchronous access to the L2 cache may encounter a
596 workaround disables the write-allocate mode for the L2 cache via the
598 may not be available in non-secure mode and thus is not available on
599 a multiplatform kernel. This should be applied by the bootloader
607 This option enables the workaround for the 742230 Cortex-A9
608 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
610 ordering of the two writes. This workaround sets a specific bit in
611 the diagnostic register of the Cortex-A9 which causes the DMB
612 instruction to behave as a DSB, ensuring the correct behaviour of
614 register may not be available in non-secure mode and thus is not
615 available on a multiplatform kernel. This should be applied by the
623 This option enables the workaround for the 742231 Cortex-A9
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
630 register of the Cortex-A9 which reduces the linefill issuing
632 diagnostics register may not be available in non-secure mode and thus
633 is not available on a multiplatform kernel. This should be applied by
641 This option enables the workaround for the 643719 Cortex-A9 (prior to
648 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
651 This option enables the workaround for the 720789 Cortex-A9 (prior to
652 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
654 As a consequence of this erratum, some TLB entries which should be
664 This option enables the workaround for the 743622 Cortex-A9
665 (r2p*) erratum. Under very rare conditions, a faulty
666 optimisation in the Cortex-A9 Store Buffer may lead to data
667 corruption. This workaround sets a specific bit in the diagnostic
668 register of the Cortex-A9 which disables the Store Buffer
672 may not be available in non-secure mode and thus is not available on a
680 This option enables the workaround for the 751472 Cortex-A9 (prior
682 completion of a following broadcasted operation if the second
683 operation is received by a CPU before the ICIALLUIS has completed,
686 not be available in non-secure mode and thus is not available on
687 a multiplatform kernel. This should be applied by the bootloader
694 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
695 r3p*) erratum. A speculative memory access may cause a page table walk
697 can populate the micro-TLB with a stale entry which may be hit with
705 This option enables the workaround for the 754327 Cortex-A9 (prior to
707 mechanism and therefore a livelock may occur if an external agent
708 continuously polls a memory location waiting to observe an update.
713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
718 hit-under-miss enabled). It sets the undocumented bit 31 in
720 register, thus disabling hit-under-miss without putting the
729 affecting Cortex-A9 MPCore with two or more processors (all
730 current revisions). Under certain timing circumstances, a data
734 system. This workaround adds a DSB instruction before the
735 relevant cache maintenance functions and sets a specific bit
742 This option enables the workaround for the 764319 Cortex-A9 erratum.
746 from a privileged mode. This work around catches the exception in a
750 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
753 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
754 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
760 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
773 This option enables the workaround for the 773022 Cortex-A15
783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
785 - Cortex-A12 852422: Execution of a sequence of instructions might
786 lead to either a data corruption or a CPU deadlock. Not fixed in
787 any Cortex-A12 cores yet.
789 Feature Register. This bit disables an optimisation applied to a
793 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
796 This option enables the workaround for the 821420 Cortex-A12
797 (all revs) erratum. In very rare timing conditions, a sequence
799 one is in the shadow of a branch or abort, can lead to a
800 deadlock when the VMOV instructions are issued out-of-order.
806 This option enables the workaround for the 825619 Cortex-A12
807 (all revs) erratum. Within rare timing constraints, executing a
808 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
809 and Device/Strongly-Ordered loads and stores might cause deadlock
815 This option enables the workaround for the 857271 Cortex-A12
817 hang. The workaround is expected to have a < 1% performance impact.
823 This option enables the workaround for the 852421 Cortex-A17
825 execution of a DMB ST instruction might fail to properly order
833 - Cortex-A17 852423: Execution of a sequence of instructions might
834 lead to either a data corruption or a CPU deadlock. Not fixed in
835 any Cortex-A17 cores yet.
836 This is identical to Cortex-A12 erratum 852422. It is a separate
844 This option enables the workaround for the 857272 Cortex-A17 erratum.
846 This is identical to Cortex-A12 erratum 857271. It is a separate
860 name of a bus system, i.e. the way the CPU talks to the other stuff
878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
888 This option should be selected by machines which have an SMP-
891 The only effect of this option is to make the SMP-related
895 bool "Symmetric Multi-Processing"
902 a system with only one CPU, say N. If you have a system with more
905 If you say N here, the kernel will run on uni- and multiprocessor
906 machines, but will use only one CPU of a multiprocessor machine. If
908 uniprocessor machines. On a uniprocessor machine, the kernel
911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
913 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
922 SMP kernels contain instructions which fail on non-SMP processors.
949 bool "Multi-core scheduler support"
952 Multi-core scheduler support improves the CPU scheduler's decision
953 making when dealing with multi-core CPU chips at a cost of slightly
961 MultiThreading at a cost of slightly increased overhead in some
982 bool "Multi-Cluster Power Management"
986 for (multi-)cluster based systems, such as big.LITTLE based
1012 transparently handle transition between a cluster of A15's
1013 and a cluster of A7's in a big.LITTLE system.
1019 This is a simple and dummy char dev interface to control
1062 int "Maximum number of CPUs (2-32)"
1070 debugging is enabled, which uses half of the per-CPU fixmap
1074 bool "Support for hot-pluggable CPUs"
1087 implementing the PSCI specification for CPU-centric power
1089 0022A ("Power State Coordination Interface System Software on
1135 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1141 Thumb-2 mode.
1169 ARM ABI (aka EABI). This is only useful if you are using a user
1185 new (ARM EABI) one. It also provides a compatibility layer to
1188 (only for non "thumb" binaries). This option adds a tiny
1189 overhead to all syscalls and produces a slightly larger kernel.
1197 to execute a legacy ABI binary then the result will be
1220 have a large amount of physical memory and/or IO, not all of the
1226 option which should result in a slightly faster kernel.
1231 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1236 For systems with a lot of processes, this can use a lot of
1239 user-space 2nd level page tables to reside in high memory.
1242 bool "Enable privileged no-access"
1248 use-after-free bugs becoming an exploitable privilege escalation
1259 Enable use of CPU domains to implement privileged no-access.
1261 CPUs with low-vector mappings use a best-efforts implementation.
1269 Enable privileged no-access by disabling TTBR0 page table walks when
1291 Disabling this is usually safe for small single-platform
1303 allocated as a single contiguous block. This option allows
1314 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1315 address divisible by 4. On 32-bit ARM processors, these non-aligned
1317 here, which has a severe performance impact. This is necessary for
1318 correct operation of some network protocols. With an IP-only
1327 cores where a 8-word STM instruction give significantly higher
1328 memory write throughput than a sequence of individual 32bit stores.
1330 A possible side effect is a slight increase in scheduling latency
1334 However, if the CPU data cache is using a write-allocate mode,
1341 under a hypervisor, potentially improving performance significantly
1351 that, there can be a small performance impact.
1371 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1374 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1377 bool "Use a unique stack canary value for each task"
1389 Enable this option to switch to a different method that uses a
1428 The physical address at which the ROM-able zImage is to be
1430 ROM-able zImage formats normally set this to a suitable
1440 for the ROM-able zImage which must be available while the
1443 Platforms which normally make use of ROM-able zImage formats
1444 normally set this to a suitable value in their defconfig file.
1460 With this option, the boot code will look for a device tree binary
1464 This is meant as a backward compatibility convenience for those
1465 systems with a bootloader that can't be upgraded to accommodate
1466 the documented boot protocol using a device tree.
1470 look like a DTB header after a reboot if no actual DTB is appended
1471 to zImage. Do not leave this option active in a production kernel
1472 if you don't intend to always append a DTB. Proper passing of the
1473 location into r2 of a bootloader provided DTB is always preferable
1480 Some old bootloaders can't be updated to a DTB capable one, yet
1483 provided by the bootloader and can't always be stored in a static
1484 DTB. To allow a device tree enabled kernel to be used with such
1496 Uses the command-line options passed by the boot loader instead of
1503 The command-line arguments provided by the boot loader will be
1514 architectures, you should supply some command-line options at build
1515 time by entering them here. As a minimum, you should specify the
1526 Uses the command-line options passed by the boot loader. If
1533 The command-line arguments provided by the boot loader will be
1542 command-line options your boot loader passes to the kernel.
1546 bool "Kernel Execute-In-Place from ROM"
1550 Execute-In-Place allows the kernel to run from non-volatile storage
1553 to RAM. Read-write sections, such as the data section and stack,
1584 copied, saving some precious ROM space. A possible drawback is a
1610 will be determined at run-time, either by masking the current IP
1628 by UEFI firmware (such as non-volatile variables, realtime
1629 clock, and platform reset). A UEFI stub is also provided to
1643 continue to boot on existing non-UEFI platforms.
1649 to be enabled much earlier than we do on ARM, which is non-trivial.
1672 your machine has an FPA or floating point co-processor podule.
1681 Say Y to include 80-bit support in the kernel floating-point
1682 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1683 Note that gcc does not generate 80-bit operations by default,
1696 It is very simple, and approximately 3-6 times faster than NWFPE.
1700 If you do not feel you need a faster FP emulation you should better
1704 bool "VFP-format floating point maths"
1708 if your hardware includes a VFP unit.
1710 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for