16 int arc_hsdk_axi_dmac_coherent __section(".data") = 0;
18 #define ARC_CCM_UNUSED_ADDR	0x60000000
21 #define ARC_PERIPHERAL_BASE	0xf0000000
22 #define CREG_BASE		(ARC_PERIPHERAL_BASE + 0x1000)
24 #define SDIO_BASE		(ARC_PERIPHERAL_BASE + 0xA000)
25 #define SDIO_UHS_REG_EXT	(SDIO_BASE + 0x108)
28 #define HSDK_GPIO_INTC          (ARC_PERIPHERAL_BASE + 0x3000)
66 	 * - GPIO[0] - Bluetooth interrupt of RS9113 module  in hsdk_enable_gpio_intc_wire()
71 	 * use-case so we only enable lines 0, 2 and 3.  in hsdk_enable_gpio_intc_wire()
75 #define GPIO_INTEN              (HSDK_GPIO_INTC + 0x30)  in hsdk_enable_gpio_intc_wire()
76 #define GPIO_INTMASK            (HSDK_GPIO_INTC + 0x34)  in hsdk_enable_gpio_intc_wire()
77 #define GPIO_INTTYPE_LEVEL      (HSDK_GPIO_INTC + 0x38)  in hsdk_enable_gpio_intc_wire()
78 #define GPIO_INT_POLARITY       (HSDK_GPIO_INTC + 0x3c)  in hsdk_enable_gpio_intc_wire()
79 #define GPIO_INT_CONNECTED_MASK	0x0d  in hsdk_enable_gpio_intc_wire()
81 	iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);  in hsdk_enable_gpio_intc_wire()
83 	iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);  in hsdk_enable_gpio_intc_wire()
84 	iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);  in hsdk_enable_gpio_intc_wire()
96 	if (node < 0)  in hsdk_tweak_node_coherency()
104 	ret = 0;  in hsdk_tweak_node_coherency()
112 		ret = fdt_setprop(fdt, node, "dma-coherent", NULL, 0);  in hsdk_tweak_node_coherency()
114 	if (ret < 0)  in hsdk_tweak_node_coherency()
117 	return 0;  in hsdk_tweak_node_coherency()
125 	M_HS_CORE = 0,
145  * AXI_M_m_SLV{0|1} - Slave Select register for master 'm'.
147  *  - 0  => no slave selected
158  * AXI_M_m_OFFSET{0|1} - Addr Offset register for master 'm'
164  * 0	HS (CBU)	0x11111111	0x63111111	0xFEDCBA98	0x0E543210
165  * 1	HS (RTT)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
166  * 2	AXI Tunnel	0x88888888	0x88888888	0xFEDCBA98	0x76543210
167  * 3	HDMI-VIDEO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
168  * 4	HDMI-ADUIO	0x77777777	0x77777777	0xFEDCBA98	0x76543210
169  * 5	USB-HOST	0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98
170  * 6	ETHERNET	0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98
171  * 7	SDIO		0x77777777	0x77999999	0xFEDCBA98	0x76DCBA98
172  * 8	GPU		0x77777777	0x77777777	0xFEDCBA98	0x76543210
173  * 9	DMAC (port #1)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
174  * 10	DMAC (port #2)	0x77777777	0x77777777	0xFEDCBA98	0x76543210
175  * 11	DVFS		0x00000000	0x60000000	0x00000000	0x00000000
178 #define CREG_AXI_M_SLV0(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m)))
179 #define CREG_AXI_M_SLV1(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))
180 #define CREG_AXI_M_OFT0(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))
181 #define CREG_AXI_M_OFT1(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
182 #define CREG_AXI_M_UPDT(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
184 #define CREG_AXI_M_HS_CORE_BOOT	((void __iomem *)(CREG_BASE + 0x010))
186 #define CREG_PAE		((void __iomem *)(CREG_BASE + 0x180))
187 #define CREG_PAE_UPDT		((void __iomem *)(CREG_BASE + 0x194))
202 		axi_m_slv1 = 0x77999999;  in hsdk_init_memory_bridge_axi_dmac()
203 		axi_m_oft1 = 0x76DCBA98;  in hsdk_init_memory_bridge_axi_dmac()
205 		axi_m_slv1 = 0x77777777;  in hsdk_init_memory_bridge_axi_dmac()
206 		axi_m_oft1 = 0x76543210;  in hsdk_init_memory_bridge_axi_dmac()
209 	writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));  in hsdk_init_memory_bridge_axi_dmac()
210 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));  in hsdk_init_memory_bridge_axi_dmac()
215 	writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));  in hsdk_init_memory_bridge_axi_dmac()
216 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));  in hsdk_init_memory_bridge_axi_dmac()
228 	 * We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first  in hsdk_init_memory_bridge()
231 	reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);  in hsdk_init_memory_bridge()
233 	writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));  in hsdk_init_memory_bridge()
234 	writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));  in hsdk_init_memory_bridge()
235 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));  in hsdk_init_memory_bridge()
236 	writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));  in hsdk_init_memory_bridge()
239 	writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));  in hsdk_init_memory_bridge()
240 	writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));  in hsdk_init_memory_bridge()
241 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));  in hsdk_init_memory_bridge()
242 	writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));  in hsdk_init_memory_bridge()
245 	writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));  in hsdk_init_memory_bridge()
246 	writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));  in hsdk_init_memory_bridge()
247 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));  in hsdk_init_memory_bridge()
248 	writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));  in hsdk_init_memory_bridge()
251 	writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));  in hsdk_init_memory_bridge()
252 	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));  in hsdk_init_memory_bridge()
253 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));  in hsdk_init_memory_bridge()
254 	writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));  in hsdk_init_memory_bridge()
257 	writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));  in hsdk_init_memory_bridge()
258 	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));  in hsdk_init_memory_bridge()
259 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));  in hsdk_init_memory_bridge()
260 	writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));  in hsdk_init_memory_bridge()
263 	writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));  in hsdk_init_memory_bridge()
264 	writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));  in hsdk_init_memory_bridge()
265 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));  in hsdk_init_memory_bridge()
266 	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));  in hsdk_init_memory_bridge()
269 	writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));  in hsdk_init_memory_bridge()
270 	writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));  in hsdk_init_memory_bridge()
271 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));  in hsdk_init_memory_bridge()
272 	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));  in hsdk_init_memory_bridge()
275 	writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));  in hsdk_init_memory_bridge()
276 	writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));  in hsdk_init_memory_bridge()
277 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));  in hsdk_init_memory_bridge()
278 	writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));  in hsdk_init_memory_bridge()
281 	writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));  in hsdk_init_memory_bridge()
282 	writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));  in hsdk_init_memory_bridge()
283 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));  in hsdk_init_memory_bridge()
284 	writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));  in hsdk_init_memory_bridge()
287 	writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));  in hsdk_init_memory_bridge()
288 	writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));  in hsdk_init_memory_bridge()
289 	writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));  in hsdk_init_memory_bridge()
290 	writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));  in hsdk_init_memory_bridge()
301 	writel(0x00000000, CREG_PAE);  in hsdk_init_memory_bridge()