arc/plat-axs10x/axs10x.c

1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
33 	 *         ---------------------  in axs10x_enable_gpio_intc_wire()
34 	 *        |  snps,arc700-intc |  in axs10x_enable_gpio_intc_wire()
35 	 *        ---------------------  in axs10x_enable_gpio_intc_wire()
37 	 * -------------------   -------------------  in axs10x_enable_gpio_intc_wire()
38 	 * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |  in axs10x_enable_gpio_intc_wire()
39 	 * -------------------   -------------------  in axs10x_enable_gpio_intc_wire()
43 	 * ------------------------  in axs10x_enable_gpio_intc_wire()
44 	 * | snps,dw-apb-intc (MB)|  in axs10x_enable_gpio_intc_wire()
45 	 * ------------------------  in axs10x_enable_gpio_intc_wire()
49 	 * Current implementation of "irq-dw-apb-ictl" driver doesn't work well  in axs10x_enable_gpio_intc_wire()
51 	 * not yet instantiated. See discussion here -  in axs10x_enable_gpio_intc_wire()
55 	 * DT hardware topology - connect MB intc directly to cpu intc  in axs10x_enable_gpio_intc_wire()
67 	iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);  in axs10x_enable_gpio_intc_wire()
70 	iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);  in axs10x_enable_gpio_intc_wire()
87 	pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,  in axs10x_print_board_ver()
97 	if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))  in axs10x_early_init()
98 		mb_rev = 3;	/* HT-3 (rev3.0) */  in axs10x_early_init()
100 		mb_rev = 2;	/* HT-2 (rev2.0) */  in axs10x_early_init()
121  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
124  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
125  * (0x0000_0000) of DDR Port 0 (slave #1)
127  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
130  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
131  * MB AXI Tunnel Master, which also has a mem map setup
133  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
134  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
142 #define AXC001_SLV_DDR_PORT0		1
148 /* MB AXI Target slaves */
150 #define AXS_MB_SLV_AXI_TUNNEL_CPU	1
155 /* MB AXI masters */
182  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
183  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
205  * memmap for MB AXI Masters
206  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
258 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);  in axs101_early_init()
260 	/* AXI tunnel memory map (incoming traffic from MB into CPU Card */  in axs101_early_init()
263 	iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);  in axs101_early_init()
278 	/* reset ethernet and ULPI interfaces */  in axs101_early_init()
293 #define AXC003_MST_HS38		1
319 					"assigned-clock-rates", NULL);  in axs103_early_init()
320 		freq = be32_to_cpu(*(u32 *)(prop->data));  in axs103_early_init()
322 		/* Patching .dtb in-place with new core clock value */  in axs103_early_init()
326 					    "assigned-clock-rates", &freq, sizeof(freq));  in axs103_early_init()
331 	/* Memory maps already config in pre-bootloader */  in axs103_early_init()
343 	/* connect ICTL - Main Board with GPIO line */  in axs103_early_init()
379  * For the VDK OS-kit, to get the offset to pid and command fields