Lines Matching full:axi

121  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
124  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
127  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
130  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
131  * MB AXI Tunnel Master, which also has a mem map setup
133  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
134  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
148 /* MB AXI Target slaves */
155 /* MB AXI masters */
182  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
183  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
205  * memmap for MB AXI Masters
206  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
260 	/* AXI tunnel memory map (incoming traffic from MB into CPU Card */  in axs101_early_init()