16 #define AXS_MB_CGU		0xE0010000
17 #define AXS_MB_CREG		0xE0011000
19 #define CREG_MB_IRQ_MUX		(AXS_MB_CREG + 0x214)
20 #define CREG_MB_SW_RESET	(AXS_MB_CREG + 0x220)
21 #define CREG_MB_VER		(AXS_MB_CREG + 0x230)
22 #define CREG_MB_CONFIG		(AXS_MB_CREG + 0x234)
24 #define AXC001_CREG		0xF0001000
25 #define AXC001_GPIO_INTC	0xF0003000
61 #define GPIO_INTEN		(AXC001_GPIO_INTC + 0x30)  in axs10x_enable_gpio_intc_wire()
62 #define GPIO_INTMASK		(AXC001_GPIO_INTC + 0x34)  in axs10x_enable_gpio_intc_wire()
63 #define GPIO_INTTYPE_LEVEL	(AXC001_GPIO_INTC + 0x38)  in axs10x_enable_gpio_intc_wire()
64 #define GPIO_INT_POLARITY	(AXC001_GPIO_INTC + 0x3c)  in axs10x_enable_gpio_intc_wire()
68 	iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);  in axs10x_enable_gpio_intc_wire()
69 	iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);  in axs10x_enable_gpio_intc_wire()
98 		mb_rev = 3;	/* HT-3 (rev3.0) */  in axs10x_early_init()
100 		mb_rev = 2;	/* HT-2 (rev2.0) */  in axs10x_early_init()
110 #define CREG_CPU_ADDR_770	(AXC001_CREG + 0x20)
111 #define CREG_CPU_ADDR_TUNN	(AXC001_CREG + 0x60)
112 #define CREG_CPU_ADDR_770_UPD	(AXC001_CREG + 0x34)
113 #define CREG_CPU_ADDR_TUNN_UPD	(AXC001_CREG + 0x74)
115 #define CREG_CPU_ARC770_IRQ_MUX	(AXC001_CREG + 0x114)
116 #define CREG_CPU_GPIO_UART_MUX	(AXC001_CREG + 0x120)
124  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
125  * (0x0000_0000) of DDR Port 0 (slave #1)
129  * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
130  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
141 #define AXC001_SLV_NONE			0
149 #define AXS_MB_SLV_NONE			0
156 #define AXS_MB_MST_TUNNEL_CPU		0
163 	{AXC001_SLV_AXI_TUNNEL,		0x0},
164 	{AXC001_SLV_AXI_TUNNEL,		0x1},
165 	{AXC001_SLV_SRAM,		0x0}, /* 0x2000_0000: Local SRAM */
166 	{AXC001_SLV_NONE,		0x0},
167 	{AXC001_SLV_NONE,		0x0},
168 	{AXC001_SLV_NONE,		0x0},
169 	{AXC001_SLV_NONE,		0x0},
170 	{AXC001_SLV_NONE,		0x0},
171 	{AXC001_SLV_DDR_PORT0,		0x0}, /* 0x8000_0000: DDR   0..256M */
172 	{AXC001_SLV_DDR_PORT0,		0x1}, /* 0x9000_0000: DDR 256..512M */
173 	{AXC001_SLV_DDR_PORT0,		0x2},
174 	{AXC001_SLV_DDR_PORT0,		0x3},
175 	{AXC001_SLV_NONE,		0x0},
176 	{AXC001_SLV_AXI_TUNNEL,		0xD},
177 	{AXC001_SLV_AXI_TUNNEL,		0xE}, /* MB: CREG, CGU... */
178 	{AXC001_SLV_AXI2APB,		0x0}, /* CPU Card local CREG, CGU... */
186 	{AXC001_SLV_AXI_TUNNEL,		0x0},
187 	{AXC001_SLV_AXI_TUNNEL,		0x1},
188 	{AXC001_SLV_SRAM,		0x0},
189 	{AXC001_SLV_NONE,		0x0},
190 	{AXC001_SLV_NONE,		0x0},
191 	{AXC001_SLV_NONE,		0x0},
192 	{AXC001_SLV_NONE,		0x0},
193 	{AXC001_SLV_NONE,		0x0},
194 	{AXC001_SLV_DDR_PORT1,		0x0},
195 	{AXC001_SLV_DDR_PORT1,		0x1},
196 	{AXC001_SLV_DDR_PORT1,		0x2},
197 	{AXC001_SLV_DDR_PORT1,		0x3},
198 	{AXC001_SLV_NONE,		0x0},
199 	{AXC001_SLV_AXI_TUNNEL,		0xD},
200 	{AXC001_SLV_AXI_TUNNEL,		0xE},
201 	{AXC001_SLV_AXI2APB,		0x0},
209 	{AXS_MB_SLV_SRAM,		0x0},
210 	{AXS_MB_SLV_SRAM,		0x0},
211 	{AXS_MB_SLV_NONE,		0x0},
212 	{AXS_MB_SLV_NONE,		0x0},
213 	{AXS_MB_SLV_NONE,		0x0},
214 	{AXS_MB_SLV_NONE,		0x0},
215 	{AXS_MB_SLV_NONE,		0x0},
216 	{AXS_MB_SLV_NONE,		0x0},
217 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0x8},	/* DDR on CPU Card */
218 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0x9},	/* DDR on CPU Card */
219 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xA},
220 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xB},
221 	{AXS_MB_SLV_NONE,		0x0},
222 	{AXS_MB_SLV_AXI_TUNNEL_HAPS,	0xD},
223 	{AXS_MB_SLV_CONTROL,		0x0},	/* MB Local CREG, CGU... */
224 	{AXS_MB_SLV_AXI_TUNNEL_CPU,	0xF},
233 	slave_select = slave_offset = 0;  in axs101_set_memmap()
234 	for (i = 0; i < 8; i++) {  in axs101_set_memmap()
239 	iowrite32(slave_select, base + 0x0);	/* SLV0 */  in axs101_set_memmap()
240 	iowrite32(slave_offset, base + 0x8);	/* OFFSET0 */  in axs101_set_memmap()
242 	slave_select = slave_offset = 0;  in axs101_set_memmap()
243 	for (i = 0; i < 8; i++) {  in axs101_set_memmap()
248 	iowrite32(slave_select, base + 0x4);	/* SLV1 */  in axs101_set_memmap()
249 	iowrite32(slave_offset, base + 0xC);	/* OFFSET1 */  in axs101_set_memmap()
270 	iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */  in axs101_early_init()
273 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);  in axs101_early_init()
276 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);  in axs101_early_init()
279 	iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);  in axs101_early_init()
282 	iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);  in axs101_early_init()
291 #define AXC003_CREG	0xF0001000
292 #define AXC003_MST_AXI_TUNNEL	0
295 #define CREG_CPU_AXI_M0_IRQ_MUX	(AXC003_CREG + 0x440)
296 #define CREG_CPU_GPIO_UART_MUX	(AXC003_CREG + 0x480)
297 #define CREG_CPU_TUN_IO_CTRL	(AXC003_CREG + 0x494)
312 	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;  in axs103_early_init()
334 	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);  in axs103_early_init()
336 	iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),  in axs103_early_init()
344 	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);  in axs103_early_init()