164 #define OP_C(x)	(((x) & 0x03f) << 6)  macro
165 #define OP_IMM	(OP_C(ARC_R_IMM))
292 #define ADDI_U6(x)	OP_C(x)
310 #define ADCI_U6(x)	OP_C(x)
329 #define SUBI_U6(x)	OP_C(x)
515 #define BTST_U6(x)	(OP_C((x) & 63))
529 #define ASLI_U6(x)	OP_C((x) & 31)
584 #define OPC_J_BLINK	(OPC_JMP | OP_C(ARC_R_BLINK))
671 	const u32 insn = OPC_MOV | OP_B(rd) | OP_C(rs);  in arc_mov_r()
708 	const u32 insn = OPC_MOV_CC | OP_B(rd) | OP_C(rs) | COND(cc);  in arc_mov_cc_r()
718 	const u32 insn = OPC_MOVU_CC | OP_B(rd) | OP_C(imm) | COND(cc);  in arc_movu_cc_r()
728 	const u32 insn = OPC_SEXB | OP_B(rd) | OP_C(rs);  in arc_sexb_r()
738 	const u32 insn = OPC_SEXH | OP_B(rd) | OP_C(rs);  in arc_sexh_r()
748 	const u32 insn = OPC_STORE | STORE_ZZ(zz) | OP_C(reg) |  in arc_st_r()
759 	const u32 insn = OPC_PUSH | OP_C(reg);  in arc_push_r()
801 	const u32 insn = OPC_ADD | OP_A(ra) | OP_B(ra) | OP_C(rc);  in arc_add_r()
811 	const u32 insn = OPC_ADDF | OP_A(ra) | OP_B(ra) | OP_C(rc);  in arc_addf_r()
853 	const u32 insn = OPC_ADC | OP_A(ra) | OP_B(ra) | OP_C(rc);  in arc_adc_r()
873 	const u32 insn = OPC_SUB | OP_A(ra) | OP_B(ra) | OP_C(rc);  in arc_sub_r()
883 	const u32 insn = OPC_SUBF | OP_A(ra) | OP_B(ra) | OP_C(rc);  in arc_subf_r()
915 	const u32 insn = OPC_SBC | OP_A(ra) | OP_B(ra) | OP_C(rc);  in arc_sbc_r()
925 	const u32 insn = OPC_CMP | OP_B(rb) | OP_C(rc);  in arc_cmp_r()
942 	const u32 insn = OPC_CMP | OP_B(rb) | OP_C(rc) | CC_equal;  in arc_cmpz_r()
962 	const u32 insn = OPC_MPY | OP_A(ra) | OP_B(rb) | OP_C(rc);  in arc_mpy_r()
984 	const u32 insn = OPC_MPYDU | OP_A(ra) | OP_B(ra) | OP_C(rc);  in arc_mpydu_r()
1006 	const u32 insn = OPC_DIVU | OP_A(rd) | OP_B(rd) | OP_C(rs);  in arc_divu_r()
1028 	const u32 insn = OPC_DIVS | OP_A(rd) | OP_B(rd) | OP_C(rs);  in arc_divs_r()
1050 	const u32 insn = OPC_REMU | OP_A(rd) | OP_B(rd) | OP_C(rs);  in arc_remu_r()
1072 	const u32 insn = OPC_REMS | OP_A(rd) | OP_B(rd) | OP_C(rs);  in arc_rems_r()
1094 	const u32 insn = OPC_AND | OP_A(rd) | OP_B(rd) | OP_C(rs);  in arc_and_r()
1116 	const u32 insn = OPC_TST | OP_B(rd) | OP_C(rs);  in arc_tst_r()
1131 	const u32 insn = OPC_TST | OP_B(rd) | OP_C(rs) | CC_equal;  in arc_tstz_r()
1140 	const u32 insn = OPC_OR | OP_A(rd) | OP_B(rs1) | OP_C(rs2);  in arc_or_r()
1160 	const u32 insn = OPC_XOR | OP_A(rd) | OP_B(rd) | OP_C(rs);  in arc_xor_r()
1180 	const u32 insn = OPC_NOT | OP_B(rd) | OP_C(rs);  in arc_not_r()
1198 	const u32 insn = OPC_ASL | OP_A(rd) | OP_B(rs1) | OP_C(rs2);  in arc_asl_r()
1216 	const u32 insn = OPC_ASR | OP_A(rd) | OP_B(rs1) | OP_C(rs2);  in arc_asr_r()
1234 	const u32 insn = OPC_LSR | OP_A(rd) | OP_B(rs1) | OP_C(rs2);  in arc_lsr_r()
1252 	const u32 insn = OPC_SWAPE | OP_B(r) | OP_C(r);  in arc_swape_r()
1268 	const u32 insn = OPC_JL | OP_C(reg);  in arc_jl()