arc/kernel/entry-arcv2.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
17 ; first 16 lines are reserved for exceptions and are not configurable.
29 # Initial 16 slots are Exception Vectors
44 VECTOR	reserved		; Reserved slots
45 VECTOR	reserved		; Reserved slots
47 # Begin Interrupt Vectors
51 VECTOR	handle_interrupt	; (19) Inter core Interrupt (IPI)
53 VECTOR	handle_interrupt	; (21) Software Triggered Intr (Self IPI)
58 .rept NR_CPU_IRQS - 8
64 reserved:  label
81 	# Note this disable is only for consistent book-keeping as further interrupts
84 	# unless this one returns (or higher prio becomes pending in 2-prio scheme)
118 ; ---------------------------------------------
120 ;   - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
122 ; ---------------------------------------------
141 	; TBD: optimize - do this only if a callee reg was involved
142 	; either a dst of emulated LD/ST or src with address-writeback
148 ; ---------------------------------------------
150 ; ---------------------------------------------
174 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)