Lines Matching +full:0 +full:x001
20 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
24 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
35 " ld.di %0, [%1] \n" \
44 " st.di %0, [%1] \n" \
71 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
72 #define ARC_REG_IC_IVIC 0x10
73 #define ARC_REG_IC_CTRL 0x11
74 #define ARC_REG_IC_IVIR 0x16
75 #define ARC_REG_IC_ENDR 0x17
76 #define ARC_REG_IC_IVIL 0x19
77 #define ARC_REG_IC_PTAG 0x1E
78 #define ARC_REG_IC_PTAG_HI 0x1F
81 #define IC_CTRL_DIS 0x1
84 #define ARC_REG_DC_BCR 0x72 /* Build Config reg */
85 #define ARC_REG_DC_IVDC 0x47
86 #define ARC_REG_DC_CTRL 0x48
87 #define ARC_REG_DC_IVDL 0x4A
88 #define ARC_REG_DC_FLSH 0x4B
89 #define ARC_REG_DC_FLDL 0x4C
90 #define ARC_REG_DC_STARTR 0x4D
91 #define ARC_REG_DC_ENDR 0x4E
92 #define ARC_REG_DC_PTAG 0x5C
93 #define ARC_REG_DC_PTAG_HI 0x5F
96 #define DC_CTRL_DIS 0x001
97 #define DC_CTRL_INV_MODE_FLUSH 0x040
98 #define DC_CTRL_FLUSH_STATUS 0x100
99 #define DC_CTRL_RGN_OP_INV 0x200
100 #define DC_CTRL_RGN_OP_MSK 0x200
103 #define ARC_REG_SLC_CFG 0x901
104 #define ARC_REG_SLC_CTRL 0x903
105 #define ARC_REG_SLC_FLUSH 0x904
106 #define ARC_REG_SLC_INVALIDATE 0x905
107 #define ARC_AUX_SLC_IVDL 0x910
108 #define ARC_AUX_SLC_FLDL 0x912
109 #define ARC_REG_SLC_RGN_START 0x914
110 #define ARC_REG_SLC_RGN_START1 0x915
111 #define ARC_REG_SLC_RGN_END 0x916
112 #define ARC_REG_SLC_RGN_END1 0x917
115 #define SLC_CTRL_DIS 0x001
116 #define SLC_CTRL_IM 0x040
117 #define SLC_CTRL_BUSY 0x100
118 #define SLC_CTRL_RGN_OP_INV 0x200
121 #define ARC_REG_IO_COH_ENABLE 0x500
122 #define ARC_IO_COH_ENABLE_BIT BIT(0)
123 #define ARC_REG_IO_COH_PARTIAL 0x501
124 #define ARC_IO_COH_PARTIAL_BIT BIT(0)
125 #define ARC_REG_IO_COH_AP0_BASE 0x508
126 #define ARC_REG_IO_COH_AP0_SIZE 0x509