boot/dts/axc003.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
14 	#address-cells = <2>;
15 	#size-cells = <2>;
18 		compatible = "simple-bus";
19 		#address-cells = <1>;
20 		#size-cells = <1>;
24 		input_clk: input-clk {
25 			#clock-cells = <0>;
26 			compatible = "fixed-clock";
27 			clock-frequency = <33333333>;
30 		core_clk: core-clk@80 {
31 			compatible = "snps,axs10x-arc-pll-clock";
33 			#clock-cells = <0>;
41 			assigned-clocks = <&core_clk>;
42 			assigned-clock-rates = <90000000>;
45 		core_intc: archs-intc@cpu {
46 			compatible = "snps,archs-intc";
47 			interrupt-controller;
48 			#interrupt-cells = <1>;
52 		 * this GPIO block ORs all interrupts on CPU card (creg,..)
55 		dw-apb-gpio@2000 {
56 			compatible = "snps,dw-apb-gpio";
58 			#address-cells = <1>;
59 			#size-cells = <0>;
61 			ictl_intc: gpio-controller@0 {
62 				compatible = "snps,dw-apb-gpio-port";
63 				gpio-controller;
64 				#gpio-cells = <2>;
65 				snps,nr-gpios = <30>;
67 				interrupt-controller;
68 				#interrupt-cells = <2>;
69 				interrupt-parent = <&core_intc>;
74 		debug_uart: dw-apb-uart@5000 {
75 			compatible = "snps,dw-apb-uart";
77 			clock-frequency = <33333000>;
78 			interrupt-parent = <&ictl_intc>;
81 			reg-shift = <2>;
82 			reg-io-width = <4>;
86 			compatible = "snps,archs-pct";
87 			#interrupt-cells = <1>;
88 			interrupt-parent = <&core_intc>;
94 	 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
97 	 * only AXS103 board has HW-coherent DMA peripherals)
98 	 * We don't need to mark pgu@17000 as dma-coherent because it uses
103 			dma-coherent;
107 			dma-coherent;
111 			dma-coherent;
115 			dma-coherent;
120 	 * The DW APB ICTL intc on MB is connected to CPU intc via a
121 	 * DT "invisible" DW APB GPIO block, configured to simply pass thru
122 	 * interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c)
125 	 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
126 	 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
132 	mb_intc: interrupt-controller@e0012000 {
133 		#interrupt-cells = <1>;
134 		compatible = "snps,dw-apb-ictl";
136 		interrupt-controller;
137 		interrupt-parent = <&core_intc>;
148 	reserved-memory {
149 		#address-cells = <2>;
150 		#size-cells = <2>;
153 		 * Move frame buffer out of IOC aperture (0x8z-0xaz).
156 			compatible = "shared-dma-pool";
158 			no-map;