Lines Matching +full:1 +full:e
15 * E - either cluster
53 and $17,255,$1 # E : 00000000000000ch
54 insbl $17,1,$2 # U : 000000000000ch00
55 bis $16,$16,$0 # E : return value
58 addq $18,$16,$6 # E : max address to write to
59 bis $1,$2,$17 # E : 000000000000chch
60 insbl $1,2,$3 # U : 0000000000ch0000
61 insbl $1,3,$4 # U : 00000000ch000000
63 or $3,$4,$3 # E : 00000000chch0000
65 xor $16,$6,$1 # E : will complete write be within one quadword?
68 or $17,$3,$17 # E : 00000000chchchch
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
71 and $16,7,$3 # E : Target addr misalignment
73 or $17,$2,$17 # E : chchchchchchchch
74 beq $1,within_quad_b # U :
75 nop # E :
82 bis $16,$16,$5 # E : Save the address
84 subq $3,8,$3 # E : Invert (for addressing uses)
86 addq $18,$3,$18 # E : $18 is new count ($3 is negative)
88 subq $16,$3,$16 # E : $16 is new aligned destination
89 bis $2,$4,$1 # E : Final bytes
92 stq_u $1,0($5) # L : Store result
104 and $18,7,$18 # E : Number of trailing bytes to write
105 bis $16,$16,$5 # E : Save dest address
119 and $16, 0x3f, $2 # E : Forward work (only useful for unrolled loop)
120 subq $3, 16, $4 # E : Only try to unroll if > 128 bytes
121 subq $2, 0x40, $1 # E : bias counter (aligning stuff 0mod64)
130 nop # E :
131 nop # E :
132 nop # E :
133 beq $1, $bigalign_b # U :
137 subq $3, 1, $3 # E : For consistency later
138 addq $1, 8, $1 # E : Increment towards zero for alignment
139 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
143 addq $5, 8, $5 # E : Inc address
144 blt $1, $alignmod64_b # U :
151 * Scratch registers available: $7, $2, $4, $1
153 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
162 subq $3, 24, $2 # E : For determining future wh64 addresses
164 nop # E :
166 addq $5, 128, $4 # E : speculative target of next wh64
169 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
173 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
178 subq $3, 16, $2 # E : Repeat the loop at least once more?
182 addq $5, 64, $5 # E :
183 subq $3, 8, $3 # E :
198 subq $3,1,$3 # E : Decrement number quads left
199 addq $5,8,$5 # E : Inc address
206 nop # E :
212 bis $2,$4,$1 # E : Put it all together
213 stq $1,0($5) # L : And back to memory
214 ret $31,($26),1 # L0 :
217 ldq_u $1,0($16) # L :
219 mskql $1,$16,$4 # U : Clear old
220 bis $2,$4,$2 # E : New result
223 mskqh $1,$6,$2 # U :
224 bis $2,$4,$1 # E :
225 stq_u $1,0($16) # L :
231 ret $31,($26),1 # L0 :
246 addq $18,$16,$6 # E : max address to write to
247 bis $16,$16,$0 # E : return value
248 xor $16,$6,$1 # E : will complete write be within one quadword?
251 bic $1,7,$1 # E : fit within a single quadword
252 beq $1,within_one_quad # U :
253 and $16,7,$3 # E : Target addr misalignment
260 bis $16,$16,$5 # E : Save the address
262 subq $3,8,$3 # E : Invert (for addressing uses)
264 addq $18,$3,$18 # E : $18 is new count ($3 is negative)
266 subq $16,$3,$16 # E : $16 is new aligned destination
267 bis $2,$4,$1 # E : Final bytes
270 stq_u $1,0($5) # L : Store result
282 and $18,7,$18 # E : Number of trailing bytes to write
283 bis $16,$16,$5 # E : Save dest address
297 and $16, 0x3f, $2 # E : Forward work (only useful for unrolled loop)
298 subq $3, 16, $4 # E : Only try to unroll if > 128 bytes
299 subq $2, 0x40, $1 # E : bias counter (aligning stuff 0mod64)
308 nop # E :
309 nop # E :
310 nop # E :
311 beq $1, $bigalign # U :
315 subq $3, 1, $3 # E : For consistency later
316 addq $1, 8, $1 # E : Increment towards zero for alignment
317 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
321 addq $5, 8, $5 # E : Inc address
322 blt $1, $alignmod64 # U :
329 * Scratch registers available: $7, $2, $4, $1
331 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
340 subq $3, 24, $2 # E : For determining future wh64 addresses
342 nop # E :
344 addq $5, 128, $4 # E : speculative target of next wh64
347 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
351 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
356 subq $3, 16, $2 # E : Repeat the loop at least once more?
360 addq $5, 64, $5 # E :
361 subq $3, 8, $3 # E :
376 subq $3,1,$3 # E : Decrement number quads left
377 addq $5,8,$5 # E : Inc address
384 nop # E :
390 bis $2,$4,$1 # E : Put it all together
391 stq $1,0($5) # L : And back to memory
392 ret $31,($26),1 # L0 :
395 ldq_u $1,0($16) # L :
397 mskql $1,$16,$4 # U : Clear old
398 bis $2,$4,$2 # E : New result
401 mskqh $1,$6,$2 # U :
402 bis $2,$4,$1 # E :
403 stq_u $1,0($16) # L :
409 ret $31,($26),1 # L0 :
426 bis $16,$16,$0 # E : return value
427 addq $18,$16,$6 # E : max address to write to
432 xor $16,$6,$1 # E : will complete write be within one quadword?
434 or $2,$5,$2 # E : 00000000c1c2c1c2
435 or $3,$4,$17 # E : c1c2c1c200000000
436 bic $1,7,$1 # E : fit within a single quadword
437 and $16,7,$3 # E : Target addr misalignment
439 or $17,$2,$17 # E : c1c2c1c2c1c2c1c2
440 beq $1,within_quad_w # U :
448 bis $16,$16,$5 # E : Save the address
450 subq $3,8,$3 # E : Invert (for addressing uses)
452 addq $18,$3,$18 # E : $18 is new count ($3 is negative)
454 subq $16,$3,$16 # E : $16 is new aligned destination
455 bis $2,$4,$1 # E : Final bytes
458 stq_u $1,0($5) # L : Store result
470 and $18,7,$18 # E : Number of trailing bytes to write
471 bis $16,$16,$5 # E : Save dest address
485 and $16, 0x3f, $2 # E : Forward work (only useful for unrolled loop)
486 subq $3, 16, $4 # E : Only try to unroll if > 128 bytes
487 subq $2, 0x40, $1 # E : bias counter (aligning stuff 0mod64)
496 nop # E :
497 nop # E :
498 nop # E :
499 beq $1, $bigalign_w # U :
503 subq $3, 1, $3 # E : For consistency later
504 addq $1, 8, $1 # E : Increment towards zero for alignment
505 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
509 addq $5, 8, $5 # E : Inc address
510 blt $1, $alignmod64_w # U :
517 * Scratch registers available: $7, $2, $4, $1
519 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
528 subq $3, 24, $2 # E : For determining future wh64 addresses
530 nop # E :
532 addq $5, 128, $4 # E : speculative target of next wh64
535 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
539 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
544 subq $3, 16, $2 # E : Repeat the loop at least once more?
548 addq $5, 64, $5 # E :
549 subq $3, 8, $3 # E :
564 subq $3,1,$3 # E : Decrement number quads left
565 addq $5,8,$5 # E : Inc address
572 nop # E :
578 bis $2,$4,$1 # E : Put it all together
579 stq $1,0($5) # L : And back to memory
580 ret $31,($26),1 # L0 :
583 ldq_u $1,0($16) # L :
585 mskql $1,$16,$4 # U : Clear old
586 bis $2,$4,$2 # E : New result
589 mskqh $1,$6,$2 # U :
590 bis $2,$4,$1 # E :
591 stq_u $1,0($16) # L :
597 ret $31,($26),1 # L0 :