Lines Matching +full:1 +full:- +full:5
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
49 * with other parts of the fall-through code. This is important, even
53 and $17,255,$1 # E : 00000000000000ch
54 insbl $17,1,$2 # U : 000000000000ch00
59 bis $1,$2,$17 # E : 000000000000chch
60 insbl $1,2,$3 # U : 0000000000ch0000
61 insbl $1,3,$4 # U : 00000000ch000000
64 inswl $17,4,$5 # U : 0000chch00000000
65 xor $16,$6,$1 # E : will complete write be within one quadword?
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
74 beq $1,within_quad_b # U :
82 bis $16,$16,$5 # E : Save the address
89 bis $2,$4,$1 # E : Final bytes
92 stq_u $1,0($5) # L : Store result
105 bis $16,$16,$5 # E : Save dest address
113 * $5 A copy of $16
121 subq $2, 0x40, $1 # E : bias counter (aligning stuff 0mod64)
133 beq $1, $bigalign_b # U :
136 stq $17, 0($5) # L :
137 subq $3, 1, $3 # E : For consistency later
138 addq $1, 8, $1 # E : Increment towards zero for alignment
139 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
143 addq $5, 8, $5 # E : Inc address
144 blt $1, $alignmod64_b # U :
148 * $3 - number quads left to go
149 * $5 - target address (aligned 0mod64)
150 * $17 - mask of stuff to store
151 * Scratch registers available: $7, $2, $4, $1
153 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
163 stq $17, 0($5) # L :
166 addq $5, 128, $4 # E : speculative target of next wh64
167 stq $17, 8($5) # L :
168 stq $17, 16($5) # L :
169 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
171 stq $17, 24($5) # L :
172 stq $17, 32($5) # L :
176 stq $17, 40($5) # L :
177 stq $17, 48($5) # L :
181 stq $17, 56($5) # L :
182 addq $5, 64, $5 # E :
197 stq $17,0($5) # L :
198 subq $3,1,$3 # E : Decrement number quads left
199 addq $5,8,$5 # E : Inc address
208 ldq $7,0($5) # L :
212 bis $2,$4,$1 # E : Put it all together
213 stq $1,0($5) # L : And back to memory
214 ret $31,($26),1 # L0 :
217 ldq_u $1,0($16) # L :
219 mskql $1,$16,$4 # U : Clear old
223 mskqh $1,$6,$2 # U :
224 bis $2,$4,$1 # E :
225 stq_u $1,0($16) # L :
231 ret $31,($26),1 # L0 :
248 xor $16,$6,$1 # E : will complete write be within one quadword?
251 bic $1,7,$1 # E : fit within a single quadword
252 beq $1,within_one_quad # U :
260 bis $16,$16,$5 # E : Save the address
267 bis $2,$4,$1 # E : Final bytes
270 stq_u $1,0($5) # L : Store result
283 bis $16,$16,$5 # E : Save dest address
291 * $5 A copy of $16
299 subq $2, 0x40, $1 # E : bias counter (aligning stuff 0mod64)
311 beq $1, $bigalign # U :
314 stq $17, 0($5) # L :
315 subq $3, 1, $3 # E : For consistency later
316 addq $1, 8, $1 # E : Increment towards zero for alignment
317 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
321 addq $5, 8, $5 # E : Inc address
322 blt $1, $alignmod64 # U :
326 * $3 - number quads left to go
327 * $5 - target address (aligned 0mod64)
328 * $17 - mask of stuff to store
329 * Scratch registers available: $7, $2, $4, $1
331 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
341 stq $17, 0($5) # L :
344 addq $5, 128, $4 # E : speculative target of next wh64
345 stq $17, 8($5) # L :
346 stq $17, 16($5) # L :
347 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
349 stq $17, 24($5) # L :
350 stq $17, 32($5) # L :
354 stq $17, 40($5) # L :
355 stq $17, 48($5) # L :
359 stq $17, 56($5) # L :
360 addq $5, 64, $5 # E :
375 stq $17,0($5) # L :
376 subq $3,1,$3 # E : Decrement number quads left
377 addq $5,8,$5 # E : Inc address
386 ldq $7,0($5) # L :
390 bis $2,$4,$1 # E : Put it all together
391 stq $1,0($5) # L : And back to memory
392 ret $31,($26),1 # L0 :
395 ldq_u $1,0($16) # L :
397 mskql $1,$16,$4 # U : Clear old
401 mskqh $1,$6,$2 # U :
402 bis $2,$4,$1 # E :
403 stq_u $1,0($16) # L :
409 ret $31,($26),1 # L0 :
417 .align 5
424 inswl $17,0,$5 # U : 000000000000c1c2
432 xor $16,$6,$1 # E : will complete write be within one quadword?
434 or $2,$5,$2 # E : 00000000c1c2c1c2
436 bic $1,7,$1 # E : fit within a single quadword
440 beq $1,within_quad_w # U :
448 bis $16,$16,$5 # E : Save the address
455 bis $2,$4,$1 # E : Final bytes
458 stq_u $1,0($5) # L : Store result
471 bis $16,$16,$5 # E : Save dest address
479 * $5 A copy of $16
487 subq $2, 0x40, $1 # E : bias counter (aligning stuff 0mod64)
499 beq $1, $bigalign_w # U :
502 stq $17, 0($5) # L :
503 subq $3, 1, $3 # E : For consistency later
504 addq $1, 8, $1 # E : Increment towards zero for alignment
505 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
509 addq $5, 8, $5 # E : Inc address
510 blt $1, $alignmod64_w # U :
514 * $3 - number quads left to go
515 * $5 - target address (aligned 0mod64)
516 * $17 - mask of stuff to store
517 * Scratch registers available: $7, $2, $4, $1
519 * CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
529 stq $17, 0($5) # L :
532 addq $5, 128, $4 # E : speculative target of next wh64
533 stq $17, 8($5) # L :
534 stq $17, 16($5) # L :
535 addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
537 stq $17, 24($5) # L :
538 stq $17, 32($5) # L :
542 stq $17, 40($5) # L :
543 stq $17, 48($5) # L :
547 stq $17, 56($5) # L :
548 addq $5, 64, $5 # E :
563 stq $17,0($5) # L :
564 subq $3,1,$3 # E : Decrement number quads left
565 addq $5,8,$5 # E : Inc address
574 ldq $7,0($5) # L :
578 bis $2,$4,$1 # E : Put it all together
579 stq $1,0($5) # L : And back to memory
580 ret $31,($26),1 # L0 :
583 ldq_u $1,0($16) # L :
585 mskql $1,$16,$4 # U : Clear old
589 mskqh $1,$6,$2 # U :
590 bis $2,$4,$1 # E :
591 stq_u $1,0($16) # L :
597 ret $31,($26),1 # L0 :