Lines Matching +full:low +full:- +full:latency

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-csum_ipv6_magic.S
4  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17  *	E	- either cluster
18  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32  * Then turn it back into a sign extended 32-bit item
35  * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36  * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
41  * add carry bits + ushort --> ushort
42  * add carry bits + ushort --> ushort (in case the carry results in an overflow)
47  * add the 3 low ushorts together, generating a uint
53  * may cause additional delay in rare cases (load-load replay traps).
64 	ldq_u	$0,0($16)	# L : Latency: 3
66 	ldq_u	$1,8($16)	# L : Latency: 3
70 	ldq_u	$5,15($16)	# L : Latency: 3
72 	ldq_u	$2,0($17)	# L : U L U L : Latency: 3
76 	ldq_u	$3,8($17)	# L : Latency: 3
80 	ldq_u	$23,15($17)	# L : Latency: 3