Lines Matching +full:1 +full:- +full:16
1 // SPDX-License-Identifier: GPL-2.0
39 irq = (vector - 0x800) >> 4; in miata_srm_device_interrupt()
47 * for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't in miata_srm_device_interrupt()
49 * vectors 0x800-0x8f0). in miata_srm_device_interrupt()
53 * So, here's this grotty hack... :-( in miata_srm_device_interrupt()
55 if (irq >= 16) in miata_srm_device_interrupt()
76 NMI (1), or EIDE (9). in miata_init_irq()
83 if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL)) in miata_init_irq()
84 pr_err("Failed to register halt-switch interrupt\n"); in miata_init_irq()
85 if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL)) in miata_init_irq()
86 pr_err("Failed to register timer-cascade interrupt\n"); in miata_init_irq()
96 * 1 NMI
102 * 7 PCI-ISA Bridge
111 *16 Interrupt Line A from slot 5
115 *20 Interrupt Line A from slot 1
116 *21 Interrupt Line B from slot 1
117 *22 Interrupt Line C from slot 1
118 *23 Interrupt Line D from slot 1
135 * 7 PCI-ISA bridge
136 * 8 PCI-PCI Bridge (SBU Riser)
144 * 13 PCI on board slot 1 (SBU Riser)
149 * This two layered interrupt approach means that we allocate IRQ 16 and
159 {16+ 8, 16+ 8, 16+ 8, 16+ 8, 16+ 8}, /* IdSel 14, DC21142 */ in miata_map_irq()
160 { -1, -1, -1, -1, -1}, /* IdSel 15, EIDE */ in miata_map_irq()
161 { -1, -1, -1, -1, -1}, /* IdSel 16, none */ in miata_map_irq()
162 { -1, -1, -1, -1, -1}, /* IdSel 17, none */ in miata_map_irq()
163 { -1, -1, -1, -1, -1}, /* IdSel 18, PCI-ISA */ in miata_map_irq()
164 { -1, -1, -1, -1, -1}, /* IdSel 19, PCI-PCI */ in miata_map_irq()
165 { -1, -1, -1, -1, -1}, /* IdSel 20, none */ in miata_map_irq()
166 { -1, -1, -1, -1, -1}, /* IdSel 21, none */ in miata_map_irq()
167 {16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 22, slot 4 */ in miata_map_irq()
168 {16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 23, slot 5 */ in miata_map_irq()
169 /* the next 7 are actually on PCI bus 1, across the bridge */ in miata_map_irq()
170 {16+11, 16+11, 16+11, 16+11, 16+11}, /* IdSel 24, QLISP/GL*/ in miata_map_irq()
171 { -1, -1, -1, -1, -1}, /* IdSel 25, none */ in miata_map_irq()
172 { -1, -1, -1, -1, -1}, /* IdSel 26, none */ in miata_map_irq()
173 { -1, -1, -1, -1, -1}, /* IdSel 27, none */ in miata_map_irq()
174 {16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 28, slot 1 */ in miata_map_irq()
175 {16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 29, slot 2 */ in miata_map_irq()
176 {16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 30, slot 3 */ in miata_map_irq()
178 { -1, -1, -1, -1, -1}, /* IdSel 31, PCI-PCI */ in miata_map_irq()
185 if((slot == 7) && (PCI_FUNC(dev->devfn) == 3)) { in miata_map_irq()
186 struct pci_dev *pdev = pci_get_slot(dev->bus, dev->devfn & ~7); in miata_map_irq()
191 return -1; in miata_map_irq()
196 return ret == PCIBIOS_SUCCESSFUL ? irq : -1; in miata_map_irq()
207 if (dev->bus->number == 0) { in miata_swizzle()
208 slot = PCI_SLOT(dev->devfn); in miata_swizzle()
210 /* Check for the built-in bridge. */ in miata_swizzle()
211 else if ((PCI_SLOT(dev->bus->self->devfn) == 8) || in miata_swizzle()
212 (PCI_SLOT(dev->bus->self->devfn) == 20)) { in miata_swizzle()
213 slot = PCI_SLOT(dev->devfn) + 9; in miata_swizzle()
217 /* Must be a card-based bridge. */ in miata_swizzle()
219 if ((PCI_SLOT(dev->bus->self->devfn) == 8) || in miata_swizzle()
220 (PCI_SLOT(dev->bus->self->devfn) == 20)) { in miata_swizzle()
221 slot = PCI_SLOT(dev->devfn) + 9; in miata_swizzle()
227 dev = dev->bus->self; in miata_swizzle()
229 slot = PCI_SLOT(dev->devfn); in miata_swizzle()
230 } while (dev->bus->self); in miata_swizzle()
252 /* Who said DEC engineers have no sense of humor? ;-) */ in miata_kill_arch()