42 	mb();  in alcor_update_irq_hw()
48 	alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));  in alcor_enable_irq()
54 	alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));  in alcor_disable_irq()
63 	*(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();  in alcor_mask_and_ack_irq()
64 	*(vuip)GRU_INT_CLEAR = 0; mb();  in alcor_mask_and_ack_irq()
73 	*(vuip)GRU_INT_CLEAR = 0x80000000; mb();  in alcor_isa_mask_and_ack_irq()
74 	*(vuip)GRU_INT_CLEAR = 0; mb();  in alcor_isa_mask_and_ack_irq()
103 			handle_irq(16 + i);  in alcor_device_interrupt()
116 	*(vuip)GRU_INT_MASK  = 0; mb();			/* all disabled */  in alcor_init_irq()
117 	*(vuip)GRU_INT_EDGE  = 0; mb();			/* all are level */  in alcor_init_irq()
118 	*(vuip)GRU_INT_HILO  = 0x80000000U; mb();	/* ISA only HI */  in alcor_init_irq()
119 	*(vuip)GRU_INT_CLEAR = 0; mb();			/* all clear */  in alcor_init_irq()
121 	for (i = 16; i < 48; ++i) {  in alcor_init_irq()
125 		if (i >= 16+20 && i <= 16+30)  in alcor_init_irq()
135 	if (request_irq(16 + 31, no_action, 0, "isa-cascade", NULL))  in alcor_init_irq()
161  *16        Interrupt Line D from slot 3
180  * This two layered interrupt approach means that we allocate IRQ 16 and 
191 		{16+13, 16+13, 16+13, 16+13, 16+13},	/* IdSel 17,  TULIP  */  in alcor_map_irq()
192 		{ 16+8,  16+8,  16+9, 16+10, 16+11},	/* IdSel 18,  slot 0 */  in alcor_map_irq()
193 		{16+16, 16+16, 16+17, 16+18, 16+19},	/* IdSel 19,  slot 3 */  in alcor_map_irq()
194 		{16+12, 16+12, 16+13, 16+14, 16+15},	/* IdSel 20,  slot 4 */  in alcor_map_irq()
196 		{ 16+0,  16+0,  16+1,  16+2,  16+3},	/* IdSel 22,  slot 2 */  in alcor_map_irq()
197 		{ 16+4,  16+4,  16+5,  16+6,  16+7},	/* IdSel 23,  slot 1 */  in alcor_map_irq()
214 			mb();  in alcor_kill_arch()