alpha/kernel/pci_impl.h

1 /* SPDX-License-Identifier: GPL-2.0 */
14  * We can't just blindly use 64K for machines with EISA busses; they
15  * may also have PCI-PCI bridges present, and then we'd configure the
20  * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
31  * a single bit set. This is so that devices like the broken Myrinet card
38  * that get passed through the PCI<->ISA bridge chip. Although this causes
39  * us to set the PCI->Mem window bases lower than normal, we still allocate
44  * We accept the risk that a broken Myrinet card will be put into a true XL
47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
58  * memory addresses.  However, we do not use them all, in order to
73 #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024)
78  * A small note about bridges and interrupts.  The DECchip 21050 (and
79  * later) adheres to the PCI-PCI bridge specification.  This says that
80  * the interrupts on the other side of a bridge are swizzled in the
108  *   Thus, each swizzle is ((pin-1) + (device#-4)) % 4
116 /* The following macro is used to implement the table-based irq mapping
117    function for all single-bus Alphas.  */
120 ({ long _ctl_ = -1; 							\
122      _ctl_ = irq_tab[slot - min_idsel][pin];				\
128 /* ??? The 8400 has a 32-byte pte entry, and the entire table apparently
131    a bit further.  Probably with per-bus operation tables.  */