95 	struct pci_controller *hose = pbus->sysdata;  in mk_conf_addr()  local
108 	addr |= hose->config_space_base;  in mk_conf_addr()
178 tsunami_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)  in tsunami_pci_tbi()  argument
180 	tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0;  in tsunami_pci_tbi()
249 	struct pci_controller *hose;  in tsunami_init_one_pchip()  local
254 	hose = alloc_pci_controller();  in tsunami_init_one_pchip()
256 		pci_isa_hose = hose;  in tsunami_init_one_pchip()
257 	hose->io_space = alloc_resource();  in tsunami_init_one_pchip()
258 	hose->mem_space = alloc_resource();  in tsunami_init_one_pchip()
264 	hose->sparse_mem_base = 0;  in tsunami_init_one_pchip()
265 	hose->sparse_io_base = 0;  in tsunami_init_one_pchip()
266 	hose->dense_mem_base  in tsunami_init_one_pchip()
268 	hose->dense_io_base  in tsunami_init_one_pchip()
271 	hose->config_space_base = TSUNAMI_CONF(index);  in tsunami_init_one_pchip()
272 	hose->index = index;  in tsunami_init_one_pchip()
274 	hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS;  in tsunami_init_one_pchip()
275 	hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE - 1;  in tsunami_init_one_pchip()
276 	hose->io_space->name = pci_io_names[index];  in tsunami_init_one_pchip()
277 	hose->io_space->flags = IORESOURCE_IO;  in tsunami_init_one_pchip()
279 	hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS;  in tsunami_init_one_pchip()
280 	hose->mem_space->end = hose->mem_space->start + 0xffffffff;  in tsunami_init_one_pchip()
281 	hose->mem_space->name = pci_mem_names[index];  in tsunami_init_one_pchip()
282 	hose->mem_space->flags = IORESOURCE_MEM;  in tsunami_init_one_pchip()
284 	if (request_resource(&ioport_resource, hose->io_space) < 0)  in tsunami_init_one_pchip()
286 	if (request_resource(&iomem_resource, hose->mem_space) < 0)  in tsunami_init_one_pchip()
322 	hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000,  in tsunami_init_one_pchip()
325         hose->sg_isa->align_entry = 4;  in tsunami_init_one_pchip()
327 	hose->sg_pci = iommu_arena_new(hose, 0x40000000,  in tsunami_init_one_pchip()
330         hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */  in tsunami_init_one_pchip()
335 	pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;  in tsunami_init_one_pchip()
336 	pchip->wsm[0].csr  = (hose->sg_isa->size - 1) & 0xfff00000;  in tsunami_init_one_pchip()
337 	pchip->tba[0].csr  = virt_to_phys(hose->sg_isa->ptes);  in tsunami_init_one_pchip()
339 	pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;  in tsunami_init_one_pchip()
340 	pchip->wsm[1].csr  = (hose->sg_pci->size - 1) & 0xfff00000;  in tsunami_init_one_pchip()
341 	pchip->tba[1].csr  = virt_to_phys(hose->sg_pci->ptes);  in tsunami_init_one_pchip()
352 	tsunami_pci_tbi(hose, 0, -1);  in tsunami_init_one_pchip()