Lines Matching +full:3 +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0
44 * BIOS32-style PCI interface:
89 * Note also that type 1 is determined by non-zero bus number.
93 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
94 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
95 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
97 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
106 * The function number selects which function of a multi-function device
118 struct pci_controller *hose = pbus->sysdata; in mk_conf_addr()
120 u8 bus = pbus->number; in mk_conf_addr()
126 if (!pbus->parent) /* No parent means peer PCI bus. */ in mk_conf_addr()
131 addr |= hose->config_space_base; in mk_conf_addr()
205 (hose->index & 1) ? TITAN_pachip1 : TITAN_pachip0; in titan_pci_tbi()
206 titan_pachip_port *port; in titan_pci_tbi() local
211 port = &pachip->g_port; in titan_pci_tbi()
212 if (hose->index & 2) in titan_pci_tbi()
213 port = &pachip->a_port; in titan_pci_tbi()
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
235 titan_query_agp(titan_pachip_port *port) in titan_query_agp() argument
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
247 titan_init_one_pachip_port(titan_pachip_port *port, int index) in titan_init_one_pachip_port() argument
254 hose->io_space = alloc_resource(); in titan_init_one_pachip_port()
255 hose->mem_space = alloc_resource(); in titan_init_one_pachip_port()
258 * This is for userland consumption. The 40-bit PIO bias that we in titan_init_one_pachip_port()
260 * based user mappings. (43-bit KSEG sign extends the physical in titan_init_one_pachip_port()
261 * address from bit 40 to hit the I/O bit - mapped addresses don't). in titan_init_one_pachip_port()
262 * So make sure we get the 43-bit PIO bias. in titan_init_one_pachip_port()
264 hose->sparse_mem_base = 0; in titan_init_one_pachip_port()
265 hose->sparse_io_base = 0; in titan_init_one_pachip_port()
266 hose->dense_mem_base in titan_init_one_pachip_port()
268 hose->dense_io_base in titan_init_one_pachip_port()
271 hose->config_space_base = TITAN_CONF(index); in titan_init_one_pachip_port()
272 hose->index = index; in titan_init_one_pachip_port()
274 hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS; in titan_init_one_pachip_port()
275 hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1; in titan_init_one_pachip_port()
276 hose->io_space->name = pci_io_names[index]; in titan_init_one_pachip_port()
277 hose->io_space->flags = IORESOURCE_IO; in titan_init_one_pachip_port()
279 hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS; in titan_init_one_pachip_port()
280 hose->mem_space->end = hose->mem_space->start + 0xffffffff; in titan_init_one_pachip_port()
281 hose->mem_space->name = pci_mem_names[index]; in titan_init_one_pachip_port()
282 hose->mem_space->flags = IORESOURCE_MEM; in titan_init_one_pachip_port()
284 if (request_resource(&ioport_resource, hose->io_space) < 0) in titan_init_one_pachip_port()
286 if (request_resource(&iomem_resource, hose->mem_space) < 0) in titan_init_one_pachip_port()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
298 saved_config[index].wsm[1] = port->wsm[1].csr; in titan_init_one_pachip_port()
299 saved_config[index].tba[1] = port->tba[1].csr; in titan_init_one_pachip_port()
301 saved_config[index].wsba[2] = port->wsba[2].csr; in titan_init_one_pachip_port()
302 saved_config[index].wsm[2] = port->wsm[2].csr; in titan_init_one_pachip_port()
303 saved_config[index].tba[2] = port->tba[2].csr; in titan_init_one_pachip_port()
305 saved_config[index].wsba[3] = port->wsba[3].csr; in titan_init_one_pachip_port()
306 saved_config[index].wsm[3] = port->wsm[3].csr; in titan_init_one_pachip_port()
307 saved_config[index].tba[3] = port->tba[3].csr; in titan_init_one_pachip_port()
312 * Note: Window 3 on Titan is Scatter-Gather ONLY. in titan_init_one_pachip_port()
314 * Window 0 is scatter-gather 8MB at 8MB (for isa) in titan_init_one_pachip_port()
316 * Window 2 is scatter-gather 1GB at 3GB in titan_init_one_pachip_port()
318 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, in titan_init_one_pachip_port()
320 hose->sg_isa->align_entry = 8; /* 64KB for ISA */ in titan_init_one_pachip_port()
322 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, in titan_init_one_pachip_port()
324 hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */ in titan_init_one_pachip_port()
326 port->wsba[0].csr = hose->sg_isa->dma_base | 3; in titan_init_one_pachip_port()
327 port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000; in titan_init_one_pachip_port()
328 port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes); in titan_init_one_pachip_port()
330 port->wsba[1].csr = __direct_map_base | 1; in titan_init_one_pachip_port()
331 port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000; in titan_init_one_pachip_port()
332 port->tba[1].csr = 0; in titan_init_one_pachip_port()
334 port->wsba[2].csr = hose->sg_pci->dma_base | 3; in titan_init_one_pachip_port()
335 port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000; in titan_init_one_pachip_port()
336 port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes); in titan_init_one_pachip_port()
338 port->wsba[3].csr = 0; in titan_init_one_pachip_port()
341 port->pctl.csr |= pctl_m_mwin; in titan_init_one_pachip_port()
344 * If it's an AGP port, initialize agplastwr. in titan_init_one_pachip_port()
346 if (titan_query_agp(port)) in titan_init_one_pachip_port()
347 port->port_specific.a.agplastwr.csr = __direct_map_base; in titan_init_one_pachip_port()
349 titan_pci_tbi(hose, 0, -1); in titan_init_one_pachip_port()
355 titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14; in titan_init_pachips()
358 titan_init_one_pachip_port(&pachip0->g_port, 0); /* hose 0 */ in titan_init_pachips()
360 titan_init_one_pachip_port(&pachip1->g_port, 1);/* hose 1 */ in titan_init_pachips()
361 titan_init_one_pachip_port(&pachip0->a_port, 2); /* hose 2 */ in titan_init_pachips()
363 titan_init_one_pachip_port(&pachip1->a_port, 3);/* hose 3 */ in titan_init_pachips()
372 printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr); in titan_init_arch()
373 printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr); in titan_init_arch()
374 printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr); in titan_init_arch()
375 printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr); in titan_init_arch()
376 printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr); in titan_init_arch()
377 printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr); in titan_init_arch()
378 printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr); in titan_init_arch()
379 printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr); in titan_init_arch()
382 printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr); in titan_init_arch()
383 printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr); in titan_init_arch()
384 printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr); in titan_init_arch()
405 titan_kill_one_pachip_port(titan_pachip_port *port, int index) in titan_kill_one_pachip_port() argument
407 port->wsba[0].csr = saved_config[index].wsba[0]; in titan_kill_one_pachip_port()
408 port->wsm[0].csr = saved_config[index].wsm[0]; in titan_kill_one_pachip_port()
409 port->tba[0].csr = saved_config[index].tba[0]; in titan_kill_one_pachip_port()
411 port->wsba[1].csr = saved_config[index].wsba[1]; in titan_kill_one_pachip_port()
412 port->wsm[1].csr = saved_config[index].wsm[1]; in titan_kill_one_pachip_port()
413 port->tba[1].csr = saved_config[index].tba[1]; in titan_kill_one_pachip_port()
415 port->wsba[2].csr = saved_config[index].wsba[2]; in titan_kill_one_pachip_port()
416 port->wsm[2].csr = saved_config[index].wsm[2]; in titan_kill_one_pachip_port()
417 port->tba[2].csr = saved_config[index].tba[2]; in titan_kill_one_pachip_port()
419 port->wsba[3].csr = saved_config[index].wsba[3]; in titan_kill_one_pachip_port()
420 port->wsm[3].csr = saved_config[index].wsm[3]; in titan_kill_one_pachip_port()
421 port->tba[3].csr = saved_config[index].tba[3]; in titan_kill_one_pachip_port()
428 titan_kill_one_pachip_port(&pachip1->g_port, 1); in titan_kill_pachips()
429 titan_kill_one_pachip_port(&pachip1->a_port, 3); in titan_kill_pachips()
431 titan_kill_one_pachip_port(&pachip0->g_port, 0); in titan_kill_pachips()
432 titan_kill_one_pachip_port(&pachip0->a_port, 2); in titan_kill_pachips()
459 unsigned long last = baddr + size - 1; in titan_ioremap()
471 h = pci_vga_hose->index; in titan_ioremap()
472 addr += pci_vga_hose->mem_space->start; in titan_ioremap()
479 for (hose = hose_head; hose; hose = hose->next) in titan_ioremap()
480 if (hose->index == h) in titan_ioremap()
486 * Is it direct-mapped? in titan_ioremap()
489 ((baddr + size - 1) < __direct_map_base + __direct_map_size)) { in titan_ioremap()
490 vaddr = addr - __direct_map_base + TITAN_MEM_BIAS; in titan_ioremap()
495 * Check the scatter-gather arena. in titan_ioremap()
497 if (hose->sg_pci && in titan_ioremap()
498 baddr >= (unsigned long)hose->sg_pci->dma_base && in titan_ioremap()
499 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){ in titan_ioremap()
504 baddr -= hose->sg_pci->dma_base; in titan_ioremap()
505 last -= hose->sg_pci->dma_base; in titan_ioremap()
507 size = PAGE_ALIGN(last) - baddr; in titan_ioremap()
518 ptes = hose->sg_pci->ptes; in titan_ioremap()
519 for (vaddr = (unsigned long)area->addr; in titan_ioremap()
525 vfree(area->addr); in titan_ioremap()
534 vfree(area->addr); in titan_ioremap()
541 vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK); in titan_ioremap()
595 return -ENOMEM; in titan_agp_setup()
599 return -ENOMEM; in titan_agp_setup()
601 aper->arena = agp->hose->sg_pci; in titan_agp_setup()
602 aper->pg_count = alpha_agpgart_size / PAGE_SIZE; in titan_agp_setup()
603 aper->pg_start = iommu_reserve(aper->arena, aper->pg_count, in titan_agp_setup()
604 aper->pg_count - 1); in titan_agp_setup()
605 if (aper->pg_start < 0) { in titan_agp_setup()
608 return -ENOMEM; in titan_agp_setup()
611 agp->aperture.bus_base = in titan_agp_setup()
612 aper->arena->dma_base + aper->pg_start * PAGE_SIZE; in titan_agp_setup()
613 agp->aperture.size = aper->pg_count * PAGE_SIZE; in titan_agp_setup()
614 agp->aperture.sysdata = aper; in titan_agp_setup()
622 struct titan_agp_aperture *aper = agp->aperture.sysdata; in titan_agp_cleanup()
625 status = iommu_release(aper->arena, aper->pg_start, aper->pg_count); in titan_agp_cleanup()
626 if (status == -EBUSY) { in titan_agp_cleanup()
628 "Attempted to release bound AGP memory - unbinding\n"); in titan_agp_cleanup()
629 iommu_unbind(aper->arena, aper->pg_start, aper->pg_count); in titan_agp_cleanup()
630 status = iommu_release(aper->arena, aper->pg_start, in titan_agp_cleanup()
631 aper->pg_count); in titan_agp_cleanup()
644 titan_pachip_port *port = agp->private; in titan_agp_configure() local
645 pctl.pctl_q_whole = port->pctl.csr; in titan_agp_configure()
647 /* Side-Band Addressing? */ in titan_agp_configure()
648 pctl.pctl_r_bits.apctl_v_agp_sba_en = agp->mode.bits.sba; in titan_agp_configure()
652 if (agp->mode.bits.rate & 2) in titan_agp_configure()
655 if (agp->mode.bits.rate & 4) in titan_agp_configure()
666 pctl.pctl_r_bits.apctl_v_agp_en = agp->mode.bits.enable; in titan_agp_configure()
671 pctl.pctl_r_bits.apctl_v_agp_sba_en ? " - SBA" : ""); in titan_agp_configure()
674 port->pctl.csr = pctl.pctl_q_whole; in titan_agp_configure()
685 struct titan_agp_aperture *aper = agp->aperture.sysdata; in titan_agp_bind_memory()
686 return iommu_bind(aper->arena, aper->pg_start + pg_start, in titan_agp_bind_memory()
687 mem->page_count, mem->pages); in titan_agp_bind_memory()
693 struct titan_agp_aperture *aper = agp->aperture.sysdata; in titan_agp_unbind_memory()
694 return iommu_unbind(aper->arena, aper->pg_start + pg_start, in titan_agp_unbind_memory()
695 mem->page_count); in titan_agp_unbind_memory()
701 struct titan_agp_aperture *aper = agp->aperture.sysdata; in titan_agp_translate()
702 unsigned long baddr = addr - aper->arena->dma_base; in titan_agp_translate()
705 if (addr < agp->aperture.bus_base || in titan_agp_translate()
706 addr >= agp->aperture.bus_base + agp->aperture.size) { in titan_agp_translate()
708 return -EINVAL; in titan_agp_translate()
711 pte = aper->arena->ptes[baddr >> PAGE_SHIFT]; in titan_agp_translate()
714 return -EINVAL; in titan_agp_translate()
735 titan_pachip_port *port; in titan_agp_info() local
736 int hosenum = -1; in titan_agp_info()
740 * Find the AGP port. in titan_agp_info()
742 port = &TITAN_pachip0->a_port; in titan_agp_info()
743 if (titan_query_agp(port)) in titan_agp_info()
747 titan_query_agp(port = &TITAN_pachip1->a_port)) in titan_agp_info()
748 hosenum = 3; in titan_agp_info()
751 * Find the hose the port is on. in titan_agp_info()
753 for (hose = hose_head; hose; hose = hose->next) in titan_agp_info()
754 if (hose->index == hosenum) in titan_agp_info()
757 if (!hose || !hose->sg_pci) in titan_agp_info()
770 agp->hose = hose; in titan_agp_info()
771 agp->private = port; in titan_agp_info()
772 agp->ops = &titan_agp_ops; in titan_agp_info()
775 * Aperture - not configured until ops.setup(). in titan_agp_info()
777 * FIXME - should we go ahead and allocate it here? in titan_agp_info()
779 agp->aperture.bus_base = 0; in titan_agp_info()
780 agp->aperture.size = 0; in titan_agp_info()
781 agp->aperture.sysdata = NULL; in titan_agp_info()
786 agp->capability.lw = 0; in titan_agp_info()
787 agp->capability.bits.rate = 3; /* 2x, 1x */ in titan_agp_info()
788 agp->capability.bits.sba = 1; in titan_agp_info()
789 agp->capability.bits.rq = 7; /* 8 - 1 */ in titan_agp_info()
794 pctl.pctl_q_whole = port->pctl.csr; in titan_agp_info()
795 agp->mode.lw = 0; in titan_agp_info()
796 agp->mode.bits.rate = 1 << pctl.pctl_r_bits.apctl_v_agp_rate; in titan_agp_info()
797 agp->mode.bits.sba = pctl.pctl_r_bits.apctl_v_agp_sba_en; in titan_agp_info()
798 agp->mode.bits.rq = 7; /* RQ Depth? */ in titan_agp_info()
799 agp->mode.bits.enable = pctl.pctl_r_bits.apctl_v_agp_en; in titan_agp_info()