1 // SPDX-License-Identifier: GPL-2.0
37  * By default, we direct-map starting at 2GB, in order to allow the
38  * maximum size direct-map window (2GB) to match the maximum amount of
41  * ISA DMA, since the maximum ISA DMA address is 2GB-1.
43  * For now, this seems a reasonable trade-off: even though most SABLEs
62  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
68  * BIOS32-style PCI interface:
109  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
111  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
121  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
123  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
132  *	The function number selects which function of a multi-function device 
133  *	(e.g., SCSI and Ethernet).
145 	u8 bus = pbus->number;  in mk_conf_addr()
157 			DBG(("mk_conf_addr: device (%d)>20, returning -1\n",  in mk_conf_addr()
159 			return -1;  in mk_conf_addr()
295 	mask = (size - 1) * 8;  in t2_read_config()
313 	mask = (size - 1) * 8;  in t2_write_config()
333 	temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);  in t2_direct_map_window1()
335 	temp = (length - 1) & 0xfff00000UL;  in t2_direct_map_window1()
354 	hose->sg_isa = iommu_arena_new(hose, base, length, SMP_CACHE_BYTES);  in t2_sg_map_window2()
355 	hose->sg_pci = NULL;  in t2_sg_map_window2()
357 	temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);  in t2_sg_map_window2()
359 	temp = (length - 1) & 0xfff00000UL;  in t2_sg_map_window2()
361 	*(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;  in t2_sg_map_window2()
364 	t2_pci_tbi(hose, 0, -1); /* flush TLB all */  in t2_sg_map_window2()
436 	hose->io_space = &ioport_resource;  in t2_init_arch()
438 	hae_mem->start = 0;  in t2_init_arch()
439 	hae_mem->end = T2_MEM_R1_MASK;  in t2_init_arch()
440 	hae_mem->name = pci_hae0_name;  in t2_init_arch()
443 	hose->mem_space = hae_mem;  in t2_init_arch()
444 	hose->index = 0;  in t2_init_arch()
446 	hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR;  in t2_init_arch()
447 	hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR;  in t2_init_arch()
448 	hose->sparse_io_base = T2_IO - IDENT_ADDR;  in t2_init_arch()
449 	hose->dense_io_base = 0;  in t2_init_arch()
452 	 * Set up the PCI->physical memory translation windows.  in t2_init_arch()
477 	 * Thus we can now run standard X servers on SABLE/LYNX. :-)  in t2_init_arch()
513 	*(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);  in t2_pci_tbi()
518 	*(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);  in t2_pci_tbi()
532 	cpu_regs->sic &= ~SIC_SEIC;  in t2_clear_errors()
535 	cpu_regs->bcce |= cpu_regs->bcce;  in t2_clear_errors()
536 	cpu_regs->cbe  |= cpu_regs->cbe;  in t2_clear_errors()
537 	cpu_regs->bcue |= cpu_regs->bcue;  in t2_clear_errors()
538 	cpu_regs->dter |= cpu_regs->dter;  in t2_clear_errors()
585 			printk("t2_machine_check(cpu%d): any_expected 0x%x -"  in t2_machine_check()
586 			       " (assumed) spurious -"  in t2_machine_check()
588 			       (unsigned int)mchk_header->code);  in t2_machine_check()
598 			printk("t2_machine_check(cpu%d): last_taken 0x%x - "  in t2_machine_check()
599 			       "unexpected mcheck - code 0x%x\n",  in t2_machine_check()
601 			       (unsigned int)mchk_header->code);  in t2_machine_check()
615 		printk("%s t2_mcheck(cpu%d): last_taken 0x%x - "  in t2_machine_check()
616 		       "any_expected 0x%x - code 0x%x\n",  in t2_machine_check()
619 		       (unsigned int)mchk_header->code);  in t2_machine_check()