27  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
72  *	23:16	bus number (8 bits = 128 possible buses)
104 	mb();  in conf_read()
108 	mb();  in conf_read()
113 	mb();  in conf_read()
117 	mb();  in conf_read()
118 	mb();  /* magic */  in conf_read()
123 		mb();  in conf_read()
126 	mb();  in conf_read()
148 	*(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();  in conf_write()
155 	mb();  in conf_write()
159 	mb();  in conf_write()
160 	mb();  /* magic */  in conf_write()
163 	mb();  in conf_write()
186 	addr = (bus << 16) | (devfn << 8) | (where);  in mk_conf_addr()
250 	mb();  in mcpcia_pci_tbi()
262 	mb();  in mcpcia_probe_hose()
263 	mb();  in mcpcia_probe_hose()
270 	mb();  in mcpcia_probe_hose()
275 	mb();  in mcpcia_probe_hose()
276 	mb();  /* magic */  in mcpcia_probe_hose()
280 		mb();  in mcpcia_probe_hose()
283 	mb();  in mcpcia_probe_hose()
285 	return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST;  in mcpcia_probe_hose()
339 	mb();  in mcpcia_pci_clr_err()
357 	mb();  in mcpcia_startup_hose()
363 	 * Window 0 is scatter-gather 8MB at 8MB (for isa)  in mcpcia_startup_hose()
393 	mb();  in mcpcia_startup_hose()
396 	mb();  in mcpcia_startup_hose()
399 	mb();  in mcpcia_startup_hose()
454 		printk("  paltmp[%d-%d] = %16lx %16lx\n",  in mcpcia_print_uncorrectable()
458 		printk("  shadow[%d-%d] = %16lx %16lx\n",  in mcpcia_print_uncorrectable()
462 	printk("  Addr of excepting instruction  = %16lx\n",  in mcpcia_print_uncorrectable()
464 	printk("  Summary of arithmetic traps    = %16lx\n",  in mcpcia_print_uncorrectable()
466 	printk("  Exception mask                 = %16lx\n",  in mcpcia_print_uncorrectable()
468 	printk("  Base address for PALcode       = %16lx\n",  in mcpcia_print_uncorrectable()
470 	printk("  Interrupt Status Reg           = %16lx\n",  in mcpcia_print_uncorrectable()
472 	printk("  CURRENT SETUP OF EV5 IBOX      = %16lx\n",  in mcpcia_print_uncorrectable()
474 	printk("  I-CACHE Reg %s parity error   = %16lx\n",  in mcpcia_print_uncorrectable()
478 	printk("  D-CACHE error Reg              = %16lx\n",  in mcpcia_print_uncorrectable()
496 	printk("  Effective VA                   = %16lx\n",  in mcpcia_print_uncorrectable()
498 	printk("  Reason for D-stream            = %16lx\n",  in mcpcia_print_uncorrectable()
500 	printk("  EV5 SCache address             = %16lx\n",  in mcpcia_print_uncorrectable()
502 	printk("  EV5 SCache TAG/Data parity     = %16lx\n",  in mcpcia_print_uncorrectable()
504 	printk("  EV5 BC_TAG_ADDR                = %16lx\n",  in mcpcia_print_uncorrectable()
506 	printk("  EV5 EI_ADDR: Phys addr of Xfer = %16lx\n",  in mcpcia_print_uncorrectable()
508 	printk("  Fill Syndrome                  = %16lx\n",  in mcpcia_print_uncorrectable()
510 	printk("  EI_STAT reg                    = %16lx\n",  in mcpcia_print_uncorrectable()
512 	printk("  LD_LOCK                        = %16lx\n",  in mcpcia_print_uncorrectable()
553 	  printk("IOD %d Register Subpacket - Bridge Base Address %16lx\n",  in mcpcia_print_system_area()
585 	mb();  in mcpcia_machine_check()
586 	mb();  /* magic */  in mcpcia_machine_check()
609 	mb();  in mcpcia_machine_check()