Lines Matching full:long
143 unsigned long bcc; long fill_00[3]; /* Backup Cache Control */
144 unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */
145 unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */
146 unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */
147 unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
148 unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */
149 unsigned long cbctl; long fill_06[3]; /* CBus Control */
150 unsigned long cbe; long fill_07[3]; /* CBus Error */
151 unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */
152 unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */
153 unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */
154 unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */
155 unsigned long sic; long fill_12[3]; /* System Interrupt Clear */
156 unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */
157 unsigned long madrl; long fill_14[3]; /* CBus Miss Address */
158 unsigned long rev; long fill_15[3]; /* CMIC Revision */
170 unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */
172 unsigned long elfmc_exc_addr; /* Addr of excepting insn. */
173 unsigned long elfmc_exc_sum; /* Summary of arith traps. */
174 unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */
175 unsigned long elfmc_iccsr; /* IBox hardware enables. */
176 unsigned long elfmc_pal_base; /* Base address for PALcode. */
177 unsigned long elfmc_hier; /* Hardware Interrupt Enable. */
178 unsigned long elfmc_hirr; /* Hardware Interrupt Request. */
179 unsigned long elfmc_mm_csr; /* D-stream fault info. */
180 unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */
181 unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */
182 unsigned long elfmc_abox_ctl; /* ABox Control Register. */
183 unsigned long elfmc_biu_stat; /* BIU Status. */
184 unsigned long elfmc_biu_addr; /* BUI Address. */
185 unsigned long elfmc_biu_ctl; /* BIU Control. */
186 unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */
187 unsigned long elfmc_fill_addr;/* Cache block which was being read. */
188 unsigned long elfmc_va; /* Effective VA of fault or miss. */
189 unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */
206 unsigned long elcmc_bcc; /* CSR 0 */
207 unsigned long elcmc_bcce; /* CSR 1 */
208 unsigned long elcmc_bccea; /* CSR 2 */
209 unsigned long elcmc_bcue; /* CSR 3 */
210 unsigned long elcmc_bcuea; /* CSR 4 */
211 unsigned long elcmc_dter; /* CSR 5 */
212 unsigned long elcmc_cbctl; /* CSR 6 */
213 unsigned long elcmc_cbe; /* CSR 7 */
214 unsigned long elcmc_cbeal; /* CSR 8 */
215 unsigned long elcmc_cbeah; /* CSR 9 */
216 unsigned long elcmc_pmbx; /* CSR 10 */
217 unsigned long elcmc_ipir; /* CSR 11 */
218 unsigned long elcmc_sic; /* CSR 12 */
219 unsigned long elcmc_adlk; /* CSR 13 */
220 unsigned long elcmc_madrl; /* CSR 14 */
221 unsigned long elcmc_crrev4; /* CSR 15 */
231 unsigned long elcm_merr; /* CSR0: Error Reg 1. */
232 unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */
233 unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */
234 unsigned long elcm_mconf; /* CSR3: Configuration. */
235 unsigned long elcm_medc1; /* CSR4: EDC Status 1. */
236 unsigned long elcm_medc2; /* CSR5: EDC Status 2. */
237 unsigned long elcm_medcc; /* CSR6: EDC Control. */
238 unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */
239 unsigned long elcm_mref; /* CSR8: Refresh Control. */
240 unsigned long elcm_filter; /* CSR9: CRD Filter Control. */
250 unsigned long elco_bcc; /* CSR 0 */
251 unsigned long elco_bcce; /* CSR 1 */
252 unsigned long elco_bccea; /* CSR 2 */
253 unsigned long elco_bcue; /* CSR 3 */
254 unsigned long elco_bcuea; /* CSR 4 */
255 unsigned long elco_dter; /* CSR 5 */
256 unsigned long elco_cbctl; /* CSR 6 */
257 unsigned long elco_cbe; /* CSR 7 */
258 unsigned long elco_cbeal; /* CSR 8 */
259 unsigned long elco_cbeah; /* CSR 9 */
260 unsigned long elco_pmbx; /* CSR 10 */
261 unsigned long elco_ipir; /* CSR 11 */
262 unsigned long elco_sic; /* CSR 12 */
263 unsigned long elco_adlk; /* CSR 13 */
264 unsigned long elco_madrl; /* CSR 14 */
265 unsigned long elco_crrev4; /* CSR 15 */
273 unsigned long elct_iocsr; /* IO Control and Status Register */
274 unsigned long elct_cerr1; /* Cbus Error Register 1 */
275 unsigned long elct_cerr2; /* Cbus Error Register 2 */
276 unsigned long elct_cerr3; /* Cbus Error Register 3 */
277 unsigned long elct_perr1; /* PCI Error Register 1 */
278 unsigned long elct_perr2; /* PCI Error Register 2 */
279 unsigned long elct_hae0_1; /* High Address Extension Register 1 */
280 unsigned long elct_hae0_2; /* High Address Extension Register 2 */
281 unsigned long elct_hbase; /* High Base Register */
282 unsigned long elct_wbase1; /* Window Base Register 1 */
283 unsigned long elct_wmask1; /* Window Mask Register 1 */
284 unsigned long elct_tbase1; /* Translated Base Register 1 */
285 unsigned long elct_wbase2; /* Window Base Register 2 */
286 unsigned long elct_wmask2; /* Window Mask Register 2 */
287 unsigned long elct_tbase2; /* Translated Base Register 2 */
288 unsigned long elct_tdr0; /* TLB Data Register 0 */
289 unsigned long elct_tdr1; /* TLB Data Register 1 */
290 unsigned long elct_tdr2; /* TLB Data Register 2 */
291 unsigned long elct_tdr3; /* TLB Data Register 3 */
292 unsigned long elct_tdr4; /* TLB Data Register 4 */
293 unsigned long elct_tdr5; /* TLB Data Register 5 */
294 unsigned long elct_tdr6; /* TLB Data Register 6 */
295 unsigned long elct_tdr7; /* TLB Data Register 7 */
302 unsigned long elcpb_biu_stat;
303 unsigned long elcpb_biu_addr;
304 unsigned long elcpb_biu_ctl;
305 unsigned long elcpb_fill_syndrome;
306 unsigned long elcpb_fill_addr;
307 unsigned long elcpb_bc_tag;
355 #define vulp volatile unsigned long *
357 extern inline u8 t2_inb(unsigned long addr) in t2_inb()
359 long result = *(vip) ((addr << 5) + T2_IO + 0x00); in t2_inb()
363 extern inline void t2_outb(u8 b, unsigned long addr) in t2_outb()
365 unsigned long w; in t2_outb()
372 extern inline u16 t2_inw(unsigned long addr) in t2_inw()
374 long result = *(vip) ((addr << 5) + T2_IO + 0x08); in t2_inw()
378 extern inline void t2_outw(u16 b, unsigned long addr) in t2_outw()
380 unsigned long w; in t2_outw()
387 extern inline u32 t2_inl(unsigned long addr) in t2_inl()
392 extern inline void t2_outl(u32 b, unsigned long addr) in t2_outl()
398 extern inline u64 t2_inq(unsigned long addr) in t2_inq()
403 extern inline void t2_outq(u64 b, unsigned long addr) in t2_outq()
445 unsigned long msb = addr >> 27; \
459 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_readb()
460 unsigned long result; in t2_readb()
470 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_readw()
471 unsigned long result; in t2_readw()
485 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_readl()
486 unsigned long result; in t2_readl()
496 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_readq()
497 unsigned long r0, r1, work; in t2_readq()
509 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_writeb()
510 unsigned long w; in t2_writeb()
520 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_writew()
521 unsigned long w; in t2_writew()
535 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_writel()
544 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; in t2_writeq()
545 unsigned long work; in t2_writeq()
554 __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr) in t2_ioportmap()
559 __EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr, in t2_ioremap()
560 unsigned long size) in t2_ioremap()
565 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr) in t2_is_ioaddr()
567 return (long)addr >= 0; in t2_is_ioaddr()
572 return (unsigned long)addr >= T2_DENSE_MEM; in t2_is_mmio()
584 return t2_in##OS((unsigned long)xaddr - T2_IO); \
591 t2_out##OS(b, (unsigned long)xaddr - T2_IO); \