include/asm/core_marvel.h

34 	ev7_csr	RBOX_CFG;		/* 0x0000 */
38 	ev7_csr	RBOX_TCTL;		/* 0x0040 */
42 	ev7_csr	RBOX_INTQ;		/* 0x0080 */
46 	ev7_csr	RBOX_SCRATCH2;		/* 0x00c0 */
56 #define EV7_PE_MASK		0x1ffUL /* 9 bits ( 256 + mem/io ) */
59 #define EV7_CSR_PHYS(pe, off)	(EV7_IPE(pe) | (0x7FFCUL << 20) | (off))
60 #define EV7_CSRS_PHYS(pe)	(EV7_CSR_PHYS(pe, 0UL))
76 	io7_csr	POx_CTRL;	       	/* 0x0000 */
80 	io7_csr	POx_MEM_ADR_EXT;	/* 0x0100 */
82 	io7_csr rsvd1[2];	/* ?? spec doesn't show 0x180 */
83 	io7_csr POx_DM_SOURCE;		/* 0x0200 */
87 	io7_csr rsvd2[4];		/* 0x0300 */
90 	io7_csr AGP_CAP_ID;		/* 0x0400 */
96 	io7_csr	POx_MONCTL;		/* 0x0500 */
100 	io7_csr POx_SCRATCH;		/* 0x0600 */
104 	io7_csr rsvd4;			/* 0x0700 */
111 	io7_csr POx_WBASE[4];		/* 0x1000 */
137 	io7_csr IO_ASIC_REV;		/* 0x30.0000 */
141 	io7_csr PO7_RST2;		/* 0x30.0100 */
146 	io7_csr IO7_ACC_CLUMP;		/* 0x30.0300 */
150 	io7_csr IO7_UPH_TO;		/* 0x30.0400 */
154 	io7_csr PO7_MONCTL;		/* 0x30.0500 */
158 	io7_csr PO7_SCRATCH;		/* 0x30.0600 */
162 	io7_csr PO7_PMASK;		/* 0x30.0700 */
166 	io7_csr PO7_ERROR_SUM;		/* 0x30.2000 */
170 	io7_csr PO7_UNCRR_SYM;		/* 0x30.2100 */
173 	io7_csr PO7_UGBGE_SYM;		/* 0x30.2200 */
175 	io7_csr PO7_LSI_CTL[128];	/* 0x31.0000 */
177 	io7_csr HLT_CTL;		/* 0x31.3ec0 */
178 	io7_csr HPI_CTL;		/* 0x31.3f00 */
182 	io7_csr PO7_MSI_CTL[16];	/* 0x31.4000 */
194 	io7_csr rsvd5[125];	    	/* 0x31.a000 */
195 	io7_csr MISC_PND;		/* 0x31.b800 */
197 	io7_csr MSI_PND[16];		/* 0x31.c000 */
199 	io7_csr MSI_CLR[16];		/* 0x31.c800 */
205 #define wbase_m_ena  0x1
206 #define wbase_m_sg   0x2
207 #define wbase_m_dac  0x4
208 #define wbase_m_addr 0xFFF00000
211 		unsigned ena : 1;	/* <0>			*/
228  *	<7:5>		<4:2>		<1:0>
232 		unsigned int_num : 9;		/* <8:0>    	*/
247 #define IO7_PORT_MASK	   	0x07UL	/* 3 bits of port 	   */
254 #define IO7_MEM_PHYS(pe, port)	(IO7_HOSE(pe, port) | 0x00000000UL)
255 #define IO7_CONF_PHYS(pe, port)	(IO7_HOSE(pe, port) | 0xFE000000UL)
256 #define IO7_IO_PHYS(pe, port)	(IO7_HOSE(pe, port) | 0xFF000000UL)
258                                 (IO7_HOSE(pe, port) | 0xFF800000UL | (off))
259 #define IO7_CSRS_PHYS(pe, port)	(IO7_CSR_PHYS(pe, port, 0UL))
260 #define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL))
269 #define IO7_PLL_RNGA(pll)	(((pll) >> 3) & 0x7)
270 #define IO7_PLL_RNGB(pll)	(((pll) >> 6) & 0x7)
286 	 (&(((io7_ioport_csrs *)IO7_CSRS_KERN(0, 0))->POx_IACK_SPECIAL)))
366 #define marvel_trivial_io_bw	0
368 #define marvel_trivial_iounmap	0