kvm/x86/msr.rst

1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 	4-byte alignment physical address of a memory area which must be
42 		An odd version indicates an in-progress update.
53 	Note that although MSRs are per-CPU entities, the effect of this
63 	4-byte aligned physical address of a memory area which must be in
80 	updates of this structure is arbitrary and implementation-dependent.
89 		An odd version indicates an in-progress update.
104 		tsc-related quantity to nanoseconds
107 		shift to be used when converting tsc-related
115 		derive per-CPU time by doing::
117 			time = (current_tsc - tsc_timestamp)
121 				time >>= -tsc_shift;
132 		+-----------+--------------+----------------------------------+
134 		+-----------+--------------+----------------------------------+
138 		+-----------+--------------+----------------------------------+
142 		+-----------+--------------+----------------------------------+
181 			return PRESENT;
185 			return PRESENT;
195 	Bits 63-6 hold 64-byte aligned physical address of a 64 byte memory area
200 		/* Used for 'page not present' events delivered via #PF */
203 		/* Used for 'page ready' events delivered via interrupt notification */
209 	Bits 5-4 of the MSR are reserved and should be zero. Bit 0 is set to 1
214 	present in CPUID. Bit 3 enables interrupt based delivery of 'page ready'
215 	events. Bit 3 can only be set if KVM_FEATURE_ASYNC_PF_INT is present in
218 	'Page not present' events are currently always delivered as synthetic
225 	with asynchronous 'page not present' event. If during a page fault APF
230 	Note, since APF 'page not present' events use the same exception vector
234 	Bytes 4-7 of 64 byte memory location ('token') will be written to by the
237 	'page not present' event. The event indicates the page is now available.
240 	clearing the location; writing to the MSR forces KVM to re-scan its
243 	Note, MSR_KVM_ASYNC_PF_INT MSR specifying the interrupt vector for 'page
245 	in MSR_KVM_ASYNC_PF_EN or interrupt #0 can get injected. The MSR is
246 	available if KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
249 	exception as 'page not present' events but this is now deprecated. If
250 	bit 3 (interrupt based delivery) is not set APF events are not delivered.
256 	same vcpu as 'page not present' event was, but guest should not rely on
263 	64-byte alignment physical address of a memory area which must be
278 	updates of this structure is arbitrary and implementation-dependent.
289 		in-progress update.
302 		not. Non-zero values mean the vCPU has been preempted. Zero
310 	Bit 0 is 1 when PV end of interrupt is enabled on the vcpu; 0
312 	interrupt is enabled (bit 0 set), bits 63-2 hold a 4-byte aligned
317 	written to by the hypervisor, typically at the time of interrupt
320 	EOI by clearing the bit in guest memory - this location will
333 	therefore to make sure hypervisor does not interrupt the
345 	Control host-side polling.
348 	Bit 0 enables (1) or disables (0) host-side HLT polling logic.
359 	Bits 0-7: APIC vector for delivery of 'page ready' APF events.
360 	Bits 8-63: Reserved
362 	Interrupt vector for asynchnonous 'page ready' notifications delivery.
365 	KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
375 	write '1' to bit 0 of the MSR, this causes the host to re-scan its queue
377 	if KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
383         This MSR is available if KVM_FEATURE_MIGRATION_CONTROL is present in