kvm/x86/msr.rst

1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 	4-byte alignment physical address of a memory area which must be
25 	in guest RAM. This memory is expected to hold a copy of the following
40 		guest has to check version before and after grabbing
42 		An odd version indicates an in-progress update.
53 	Note that although MSRs are per-CPU entities, the effect of this
63 	4-byte aligned physical address of a memory area which must be in
64 	guest RAM, plus an enable bit in bit 0. This memory is expected to hold
80 	updates of this structure is arbitrary and implementation-dependent.
87 		guest has to check version before and after grabbing
89 		An odd version indicates an in-progress update.
104 		tsc-related quantity to nanoseconds
107 		shift to be used when converting tsc-related
115 		derive per-CPU time by doing::
117 			time = (current_tsc - tsc_timestamp)
121 				time >>= -tsc_shift;
127 		coordinated between the guest and the hypervisor. Availability
132 		+-----------+--------------+----------------------------------+
134 		+-----------+--------------+----------------------------------+
138 		+-----------+--------------+----------------------------------+
139 		|	    |		   | guest vcpu has been paused by    |
142 		+-----------+--------------+----------------------------------+
195 	Bits 63-6 hold 64-byte aligned physical address of a 64 byte memory area
196 	which must be in guest RAM. This memory is expected to hold the
209 	Bits 5-4 of the MSR are reserved and should be zero. Bit 0 is set to 1
220 	a token that will be used to notify the guest when missing page becomes
224 	is currently supported, when set, it indicates that the guest is dealing
226 	'flags' is '0' it means that this is regular page fault. Guest is
231 	as regular page fault, guest must reset 'flags' to '0' before it does
234 	Bytes 4-7 of 64 byte memory location ('token') will be written to by the
238 	Guest is supposed to write '0' to 'token' when it is done handling
240 	clearing the location; writing to the MSR forces KVM to re-scan its
256 	same vcpu as 'page not present' event was, but guest should not rely on
263 	64-byte alignment physical address of a memory area which must be
264 	in guest RAM, plus an enable bit in bit 0. This memory is expected to
278 	updates of this structure is arbitrary and implementation-dependent.
280 	anything with bit0 == 0 is written to it. Guest is required to make sure
286 		a sequence counter. In other words, guest has to check
289 		in-progress update.
302 		not. Non-zero values mean the vCPU has been preempted. Zero
312 	interrupt is enabled (bit 0 set), bits 63-2 hold a 4-byte aligned
313 	physical address of a 4 byte memory area which must be in guest RAM and
318 	injection.  Value of 1 means that guest can skip writing EOI to the apic
320 	EOI by clearing the bit in guest memory - this location will
324 	It is always safe for the guest to ignore the optimization and perform
329 	guest does not need to use either lock prefix or memory ordering
334 	guest and clear the least significant bit in the memory area
335 	in the window between guest testing it to detect
336 	whether it can skip EOI apic write and between guest
338 	guest must both read the least significant bit in the memory area and
345 	Control host-side polling.
348 	Bit 0 enables (1) or disables (0) host-side HLT polling logic.
359 	Bits 0-7: APIC vector for delivery of 'page ready' APF events.
360 	Bits 8-63: Reserved
373 	When the guest is done processing 'page ready' APF event and 'token'
375 	write '1' to bit 0 of the MSR, this causes the host to re-scan its queue
384         CPUID.  Bit 0 represents whether live migration of the guest is allowed.
386         When a guest is started, bit 0 will be 0 if the guest has encrypted
387         memory and 1 if the guest does not have encrypted memory.  If the
388         guest is communicating page encryption status to the host using the
390         allow live migration of the guest.