kvm/devices/mpic.rst

1 .. SPDX-License-Identifier: GPL-2.0
9   - KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0
10   - KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2
20     KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25   KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27     "attr" is the byte offset into the MPIC register space.  Accesses
28     must be 4-byte aligned.
33   KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37     For edge-triggered interrupts:  Writing 1 is considered an activating
38     edge, and writing 0 is ignored.  Reading returns 1 if a previously
39     signaled edge has not been acknowledged, and 0 otherwise.
42     byte offset of the relevant IVPR from EIVPR0, divided by 32.
53   The numbering is the same as the MPIC device tree binding -- based on
54   the register offset from the beginning of the sources array, without
58   Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.