kvm/devices/arm-vgic-v3.rst

1 .. SPDX-License-Identifier: GPL-2.0
9   - KVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23     KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28     KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35     KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38         bits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
41       - index encodes the unique redistributor region index
42       - flags: reserved for future use, currently 0
43       - base field encodes bits [51:16] of the guest physical base address
45       - count encodes the number of redistributors in the region. Must be
72     -E2BIG   Address outside of addressable IPA range
73     -EINVAL  Incorrectly aligned address, bad redistributor region
75     -EEXIST  Address already configured
76     -ENOENT  Attempt to read the characteristics of a non existing
78     -ENXIO   The group or attribute is unknown/unsupported for this device
80     -EFAULT  Invalid user pointer for attr->addr.
92     All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
93     __u32 value.  64-bit registers must be accessed by separately accessing the
96     Writes to read-only registers are ignored by the kernel.
102     The offset is relative to the "[Re]Distributor base address" as defined
108     architecturally defined behavior to allow software a full view of the
115     architecture defined MPIDR, and the field is encoded as follows::
131     The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
135     registers simply sets the non-reserved bits to the value written.
161     and restore the entire GIC internal state (which is defined by the
173     -ENXIO  Getting or setting this register is not yet supported
174     -EBUSY  One or more VCPUs are running
187     architecture defined MPIDR, and the field is encoded as follows::
193     defined in the A64 instruction set encoding for system register access
199     All system regs accessed through this API are (rw, 64-bit) and
206     Error -ENXIO is returned when accessed in AArch32 mode.
211     -ENXIO   Getting or setting this register is not yet supported
212     -EBUSY   VCPU is running
213     -EINVAL  Invalid mpidr or register value supplied
228     -EINVAL  Value set is out of the expected range
229     -EBUSY   Value has already be set.
247     -ENXIO   VGIC not properly configured as required prior to calling
249     -ENODEV  no online VCPU
250     -ENOMEM  memory shortage when allocating vgic internal data
251     -EFAULT  Invalid guest ram access
252     -EBUSY   One or more VCPUS are running
281     supported, will be RAZ/WI.  LPIs are always edge-triggered and are
288     architecture defined MPIDR, and the field is encoded as follows::
296     -EINVAL  vINTID is not multiple of 32 or info field is