Lines Matching full:mosi
15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
57 Some chips eliminate a signal line by combining MOSI and MISO, and
184 MOSI, and MISO.
506 SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
635 MOSI XXX__________ _______ _______ ________XXX
654 MOSI idle state configuration
658 MOSI line when the controller is not clocking out data. However, there do exist
659 peripherals that require specific MOSI line state when data is not being clocked
660 out. For example, if the peripheral expects the MOSI line to be high when the
674 MOSI _____ _______ _______ _______________ ___
688 In this extension to the usual SPI protocol, the MOSI line state is specified to
696 of their ``struct spi_controller``. The configuration to idle MOSI low is