ethernet/stmicro/stmmac.rst

1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
36 Enterprise MAC - 100G Ethernet MAC.
43 +-------------------------------+--------------+--------------+--------------+
47 +-------------------------------+--------------+--------------+--------------+
48 | Ethernet Quality-of-Service   | 4.00a        | N/A          | GMAC4+       |
49 +-------------------------------+--------------+--------------+--------------+
50 | XGMAC - 10G Ethernet MAC      | 2.10a        | N/A          | XGMAC2+      |
51 +-------------------------------+--------------+--------------+--------------+
52 | XLGMAC - 100G Ethernet MAC    | 2.00a        | N/A          | XLGMAC2+     |
53 +-------------------------------+--------------+--------------+--------------+
63  - GMII/MII/RGMII/SGMII/RMII/XGMII/XLGMII Interface
64  - Half-Duplex / Full-Duplex Operation
65  - Energy Efficient Ethernet (EEE)
66  - IEEE 802.3x PAUSE Packets (Flow Control)
67  - RMON/MIB Counters
68  - IEEE 1588 Timestamping (PTP)
69  - Pulse-Per-Second Output (PPS)
70  - MDIO Clause 22 / Clause 45 Interface
71  - MAC Loopback
72  - ARP Offloading
73  - Automatic CRC / PAD Insertion and Checking
74  - Checksum Offload for Received and Transmitted Packets
75  - Standard or Jumbo Ethernet Packets
76  - Source Address Insertion / Replacement
77  - VLAN TAG Insertion / Replacement / Deletion / Filtering (HASH and PERFECT)
78  - Programmable TX and RX Watchdog and Coalesce Settings
79  - Destination Address Filtering (PERFECT)
80  - HASH Filtering (Multicast)
81  - Layer 3 / Layer 4 Filtering
82  - Remote Wake-Up Detection
83  - Receive Side Scaling (RSS)
84  - Frame Preemption for TX and RX
85  - Programmable Burst Length, Threshold, Queue Size
86  - Multiple Queues (up to 8)
87  - Multiple Scheduling Algorithms (TX: WRR, DWRR, WFQ, SP, CBS, EST, TBS;
89  - Flexible RX Parser
90  - TCP / UDP Segmentation Offload (TSO, USO)
91  - Split Header (SPH)
92  - Safety Features (ECC Protection, Data Parity Protection)
93  - Selftests using Ethtool
99  - ``CONFIG_STMMAC_PLATFORM``: is to enable the platform driver.
100  - ``CONFIG_STMMAC_PCI``: is to enable the pci driver.
119 --------
120 :Valid Range: 5000-None
126 -----
127 :Valid Range: 0-16 (0=none,...,16=all)
134 -------
135 :Valid Range: 0-31
136 :Default Value: -1
141 ---------
142 :Valid Range: 0-3 (0=off,1=rx,2=tx,3=rx/tx)
148 -----
149 :Valid Range: 0-65535
155 --
156 :Valid Range: 64-256
162 ------
163 :Valid Range: 1536-16384
169 ---------
170 :Valid Range: 0-None
176 ----------
177 :Valid Range: 0-1 (0=off,1=on)
187 ----------------
194 the ``net_device`` structure, enabling the scatter-gather feature. This is
201 ---------------
211 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
212 buffers in order to avoid the memcpy (zero-copy).
215 --------------------
224 ---
230 ---------------
236 linked-list(CHAINED) mode. In RING each descriptor points to two data buffer
245 --------------------
255 ---------------
260     ethtool -S ethX
265     ethtool -t ethX
268 ---------------------------------
274 -----------
292 -------------------------
301 save power during the period of low-link utilization. The MAC controls whether
312 -----------------------------
314 The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP), which
318 In addition to the basic timestamp features mentioned in IEEE 1588-2002
320 IEEE 1588-2008 can be enabled when configuring the Kernel.
323 -------------------
326 available at run-time by looking at the HW capability register. This means
327 that the stmmac can manage auto-negotiation and link status w/o using the
330 registers, it is possible to look at the Auto-negotiated Link Parter Ability.
333 --------
339 --------------------
341 Several information can be passed through the platform and device-tree.
351 2) PHY Physical Address. If set to -1 the driver will pick the first PHY it
385 11) Some HWs are not able to perform the csum in HW for over-sized frames due
424 22) Use the specified TX and RX scheduling algorithm::
607 1) Mode to use (DCB or AVB)::
638 2) Mode to use (DCB or AVB)::
659 -----------------------
665 ---------------
668 register, many configurations are discovered at run-time for example to
683 using: ``ethtool -S ethX`` (that shows the Management counters (MMC) if
684 supported) or sees the MAC/DMA registers: e.g. using: ``ethtool -d ethX``
689  - ``descriptors_status``: To show the DMA TX/RX descriptor rings
690  - ``dma_cap``: To show the HW Capabilities