Documentation/mm/memory-model.rst

1 .. SPDX-License-Identifier: GPL-2.0
9 spans a contiguous range up to the maximal address. It could be,
11 for the CPU. Then there could be several contiguous ranges at
23 Regardless of the selected memory model, there exists one-to-one
35 non-NUMA systems with contiguous, or mostly contiguous, physical
54 straightforward: `PFN - ARCH_PFN_OFFSET` is an index to the
65 as hot-plug and hot-remove of the physical memory, alternative memory
66 maps for non-volatile memory devices and deferred initialization of
85    NR\_MEM\_SECTIONS = 2 ^ {(MAX\_PHYSMEM\_BITS - SECTION\_SIZE\_BITS)}
87 The `mem_section` objects are arranged in a two-dimensional array
104 corresponding `struct page` - a "classic sparse" and "sparse
108 The classic sparse encodes the section number of a page in page->flags
114 page *vmemmap` pointer that points to a virtually contiguous array of
130 for persistent memory devices in pre-allocated storage on those
158 this lack of user-api constraint to allow sub-section sized memory
159 ranges to be specified to :c:func:`arch_add_memory`, the top-half of
160 memory hotplug. Sub-section support allows for 2MB as the cross-arch
165 * pmem: Map platform persistent memory to be used as a direct-I/O target
168 * hmm: Extend `ZONE_DEVICE` with `->page_fault()` and `->page_free()`
169   event callbacks to allow a device-driver to coordinate memory management
170   events related to device-memory, typically GPU memory. See
174   PCI/-E topology to coordinate direct-DMA operations between themselves,