Lines Matching +full:single +full:- +full:channel
1 .. SPDX-License-Identifier: GPL-2.0
26 ----
37 Channel Doorbell array: Channel Doorbell (DB) registers used by the host to
48 ---------------
55 Channel context array: All channel configurations are organized in channel
58 Transfer rings: Used by the host to schedule work items for a channel. The
74 --------
82 bidirectional data pipe, which can be used by the upper-layer protocols to
84 diagnostics messages, and so on). Each channel is associated with a single
88 --------------
92 defined for each channel between the device and host and reside in the host
95 [Read Pointer (RP)] ----------->[Ring Element] } TD
96 [Write Pointer (WP)]- [Ring Element]
97 - [Ring Element]
98 --------->[Ring Element]
105 channel context.
111 associated channel DB.
114 -----------
122 [Read Pointer (RP)] ----------->[Ring Element] } ED
123 [Write Pointer (WP)]- [Ring Element]
124 - [Ring Element]
125 --------->[Ring Element]
132 channel context.
141 ------------
143 A Ring Element is a data structure used to transfer a single block
145 single buffer pointer, the size of the buffer, and additional control
147 information. For single buffer operations, a ring descriptor is composed of a
148 single element. For large multi-buffer operations (such as scatter and gather),
155 ----------
159 MHI is in reset state after power-up or hardware reset. The host is not allowed
170 issuing channel start command.
188 ------------------
191 In the case of PCIe, the device is enumerated and assigned BAR-0 for
195 * Allocates the MHI context for event, channel and command arrays.
202 -----------------
209 * Host increments the WP of the corresponding channel transfer ring.
210 * Host rings the channel DB register.