amdgpu/display/dcn-overview.rst

10 .. kernel-figure:: dc_pipeline_overview.svg
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
20   processing such as color space conversion, linearization of pixel data, tone
24   multiple planes, using global or per-pixel alpha.
26 * **Output Pixel Processing (OPP)**: Process and format pixels to be sent to
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
66 1. Pixel data interface (red): Represents the pixel data flow;
79 that HUBP accesses a surface using a specific format read from memory, and our
84 ----------------------
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
102 is to change, blend and compose pixel data, while BE's job is to frame a
103 generic pixel stream to a specific display's pixel stream.
106 ---------
108 Initially, data is passed in from VRAM through Data Fabric (DF) in native pixel
109 formats. Such data format stays through till HUBP in DCHUB, where HUBP unpacks
110 different pixel formats and outputs them to DPP in uniform streams through 4
114 representation and convert them to a DCN specific floating-point format (i.e.,
115 different from the IEEE floating-point format). In the process, CNVC also
116 applies a degamma function to transform the data from non-linear to linear
117 space to relax the floating-point calculations following. Data would stay in
118 this floating-point format from DPP to OPP.
123 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
125 Eventually, we output data in integer format at DIO.
128 ---------------------
142 .. kernel-figure:: pipeline_4k_no_split.svg
145 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
146 this log can help us to see part of this pipeline behavior in real-time::
148  HUBP:  format  addr_hi  width  height ...
164 .. kernel-figure:: pipeline_4k_split.svg
168  HUBP:  format  addr_hi  width  height ...
187 -----------
194 in order to support outputs that need a very high pixel clock, or for
203 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
215 Since DCN hardware is double-buffered the DC driver is able to program the
220 .. kernel-figure:: global_sync_vblank.svg
226 updates, i.e. it allows for multiple re-configurations between VUpdate
230 .. kernel-figure:: config_example.svg