Lines Matching refs:Feature

2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
20 Device Feature List (DFL) Overview
22 Device Feature List (DFL) defines a linked list of feature headers within the
32  +----------+  |   | Feature  |  |   | Feature  |  |   | Feature  |
38  +----------+  |   | Feature  |      | Feature  |      | Feature  |
66 Feature Header (Next_DFH) pointer.
68 Each FIU, AFU and Private Feature could implement its own functional registers.
70 e.g. FME Header Register Set, and the one for Private Feature, is named as
71 Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
73 This Device Feature List provides a way of linking features together, it's
78 Device Feature Header - Version 0
80 Version 0 (DFHv0) is the original version of the Device Feature Header.
97   * EOL - Set if the DFH is the end of the Device Feature List (DFL).
115 Device Feature Header - Version 1
117 Version 1 (DFHv1) of the Device Feature Header adds the following functionality:
125 The format of Version 1 of the Device Feature Header (DFH) is shown below::
156   * EOL - Set if the DFH is the end of the Device Feature List (DFL).
308                  | FPGA Container Device |    Device Feature List
322 given Device Feature Lists and create platform devices for feature devices
379 Feature Lists, as illustrated below:
621 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)