Documentation/fpga/dfl.rst

17 enables system level management functions such as FPGA reconfiguration.
71 Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
199 The FPGA Management Engine performs reconfiguration and other infrastructure
281   reset at any time, e.g. during DMA or Partial Reconfiguration. But it should
342 	b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
346 	   reconfiguration of the PR bitstream to the given port.
360 Partial Reconfiguration
363 reconfiguration of a PR bitstream file. The PR bitstream file must have been
365 (port) of the FPGA, otherwise, the reconfiguration operation will fail and
369 userspace before calling the reconfiguration IOCTL.
621 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
685 FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
686 to user now. In the future, if unified user interfaces for reconfiguration are