Lines Matching full:pipes

17   -- Seekable pipes
23   -- Channels, pipes, and the message channel
85 project to another (the number of data pipes needed in each direction and
90 Xillybus presents independent data streams, which resemble pipes or TCP/IP
125 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
128 The driver and hardware are designed to behave sensibly as pipes, including:
138 device files are treated like two independent pipes (except for sharing a
144 Xillybus pipes are configured (on the IP core) to be either synchronous or
154 For FPGA to host pipes, asynchronous pipes allow data transfer from the FPGA
156 has been requested by a read() call. On synchronous pipes, only the amount
159 In summary, for synchronous pipes, data between the host and FPGA is
169 Seekable pipes
228   Seekable pipes above.
256 Channels, pipes, and the message channel
259 Each of the (possibly bidirectional) pipes presented to the user is allocated
261 and pipes is necessary only because of channel 0, which is used for interrupt-
302 Note that the issue of partial buffer flushing is irrelevant for pipes having
303 the "synchronous" attribute nonzero, since synchronous pipes don't allow data
313 with no issues. Writing single bytes to pipes with 16 or 32 bit granularity
327 As mentioned earlier, the number of pipes that are created when the driver
357 the IDT. The driver relies on a rule that the pipes are sorted with decreasing