media/drivers/ipu6.rst

1 .. SPDX-License-Identifier: GPL-2.0
12 Intel IPU6 is the sixth generation of Intel Image Processing Unit used in some
14 Meteor Lake. IPU6 consists of two major systems: Input System (ISYS) and
34 ------------------------
51 ---------
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66 (CSE) to complete authentication process. The CSE is responsible of
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
93 levels of page lookup tables stored in system memory which are maintained by the
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
101 .. code-block:: none
113 	  generic PCI DMA ops to ask IOMMU to do the additional mapping if VT-d
121 component includes 3 entries - manifest, metadata and module data. Manifest and
123 specific to IPU6 which holds the binary data of firmware called package
124 directory. The IPU6 driver (``ipu6-cpd.c`` in particular) parses and validates
125 the CPD firmware file and gets the package directory binary data of the IPU6
126 firmware, copies it to specific DMA buffer and sets its base address to Buttress
135 inter-processor communication mechanism between the IPU scalar processors and
136 the CPU. There are a number of resources shared between firmware and software.
139 with a configurable number of tokens (messages). There are also common IPU6 MMIO
141 function as producer and consumer of tokens in the queues and update the write
144 The IPU6 driver must prepare and configure the number of input and output
145 queues, configure the count of tokens per queue and the size of per token before
147 must use same configurations. The IPU6 Buttress has a number of firmware boot
148 parameter registers which can be used to store the address of configuration and
155 IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers.  It can
156 capture image pixel data from camera sensors or other MIPI CSI-2 output devices.
158 D-PHYs and CSI-2 ports lane mapping
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161 The IPU6 integrates different D-PHY IPs on different SoCs, on Tiger Lake and
162 Alder Lake, IPU6 integrates MCD10 D-PHY, IPU6SE on Jasper Lake integrates JSL
163 D-PHY and IPU6EP on Meteor Lake integrates a Synopsys DWC D-PHY. There is an
164 adaptional layer between D-PHY and CSI-2 receiver controller which includes port
165 configuration, PHY wrapper or private test interfaces for D-PHY. There are 3
166 D-PHY drivers ``ipu6-isys-mcd-phy.c``, ``ipu6-isys-jsl-phy.c`` and
167 ``ipu6-isys-dwc-phy.c`` program the above 3 D-PHYs in IPU6.
169 Different IPU6 versions have different D-PHY lanes mappings, On Tiger Lake,
170 there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
171 see the PPI mmapping in ``ipu6-isys-mcd-phy.c`` for more information. On Jasper
172 Lake and Alder Lake, D-PHY has 8 data lanes and 4 clock lanes, the IPU6 supports
173 maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
174 lanes so IPU6 support maximum 6 CSI-2 ports.
176 .. Note:: Each pair of CSI-2 two ports is a single unit that can share the data
177 	  lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
178 	  maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
179 	  port 0 with 2 data lanes can work together with CSI-2 port 1 with 2
180 	  data lanes. If trying to use CSI-2 port 0 with 4 lanes, CSI-2 port 1
181 	  will not be available as the 4 data lanes are shared by CSI-2 port 0
182 	  and 1. The same applies to CSI ports 2/3, 4/5 and 7/8.
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187 The IPU6 firmware implements a series of ABIs for software access. In general,
192 resolution and data type of input source, output pin ``struct