Lines Matching +full:1 +full:- +full:1
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
13 # v1.1 defined in version 1.1
23 - e GRBG 0
24 - e RGGB 1
25 - e BGGR 2
26 - e GBRG 3
28 - e v1_0 0x10
29 - e v1_1 0x11
30 - f major 4 7
31 - f minor 0 3
39 - f 0 2
40 - e ts 0
41 - e es 1
42 - e cs 2
43 - e mp 3
53 - e 2-byte 1
54 - e 4-byte 2
56 - f rows 0 3
57 - f columns 4 7
59 - l n 0 14 2
60 - f pixels 0 11
61 - f pcode 12 15
62 - e embedded 1
63 - e dummy_pixel 2
64 - e black_pixel 3
65 - e dark_pixel 4
66 - e visible_pixel 5
67 - e manuf_specific_0 8
68 - e manuf_specific_1 9
69 - e manuf_specific_2 10
70 - e manuf_specific_3 11
71 - e manuf_specific_4 12
72 - e manuf_specific_5 13
73 - e manuf_specific_6 14
75 - l n 0 7 4
76 - f pixels 0 15
77 - f pcode 28 31
78 - e embedded 1
79 - e dummy_pixel 2
80 - e black_pixel 3
81 - e dark_pixel 4
82 - e visible_pixel 5
83 - e manuf_specific_0 8
84 - e manuf_specific_1 9
85 - e manuf_specific_2 10
86 - e manuf_specific_3 11
87 - e manuf_specific_4 12
88 - e manuf_specific_5 13
89 - e manuf_specific_6 14
93 - e global 0
94 - e alternate_global 2
103 analog_linear_gain_min 0x0094 16 v1.1
104 analog_linear_gain_max 0x0096 16 v1.1
105 analog_linear_gain_step_size 0x0098 16 v1.1
106 analog_exponential_gain_min 0x009a 16 v1.1
107 analog_exponential_gain_max 0x009c 16 v1.1
108 analog_exponential_gain_step_size 0x009e 16 v1.1
112 - e normal 1
113 - e extended 2
115 - f rows 0 3
116 - f columns 4 7
118 - l n 0 15 2
119 - f compressed 0 7
120 - f uncompressed 8 15
122 # general set-up registers
124 - e software_standby 0
125 - e streaming 1
127 - b horizontal_mirror 0
128 - b vertical_flip 1
130 - e off 0
131 - e on 1
134 - e allow 0
135 - e mask 1
137 - e complete_frames 0
138 - e frame_truncation 1
141 - b enable 0
142 - b ack 1
146 - e csi_2_dphy 2
147 - e csi_2_cphy 3
155 - e global 0
156 - e alternate 1
158 emb_data_ctrl 0x0122 v1.1
159 - b raw8_packing_for_raw16 0
160 - b raw10_packing_for_raw20 1
161 - b raw12_packing_for_raw24 2
166 - b enable 0
176 analog_linear_gain_global 0x0206 16 v1.1
177 analog_exponential_gain_global 0x0208 16 v1.1
187 - b enabled 0
188 - b separate_analog_gain 1
189 - b upscaling 2
190 - b reset_sync 3
191 - b timing_mode 4
192 - b exposure_ctrl_direct 5
193 - b separate_digital_gain 6
195 - f row 0 3
196 - f column 4 7
200 Short_analog_linear_gain_global 0x0226 16 v1.1
201 Short_analog_exponential_gain_global 0x0228 16 v1.1
203 # clock set-up registers
215 - f 0 0
216 - e single 0
217 - e dual 1
218 op_pix_clk_div_rev 0x0312 16 v1.1
219 op_sys_clk_div_rev 0x0314 16 v1.1
235 - b automatic 0
237 - b manual_readout 0
238 - b delayed_exposure 1
240 - b manual_readout_start 0
243 # sub-sampling registers
250 monochrome_en 0x0390 v1.1
251 - e enabled 0
255 - e no_scaling 0
256 - e horizontal 1
266 - e none 0
267 - e dpcm_pcm_simple 1
271 - e none 0
272 - e solid_color 1
273 - e color_bars 2
274 - e fade_to_grey 3
275 - e pn9 4
276 - e color_tile 5
294 - e auto 0
295 - e UI 1
296 - e manual 2
310 DPHY_equalization_mode 0x0824 8 v1.1
311 - b eq2 0
312 PHY_equalization_ctrl 0x0825 8 v1.1
313 - b enable 0
315 # d-phy preamble control registers
316 DPHY_preamble_ctrl 0x0826 8 v1.1
317 - b enable 0
318 DPHY_preamble_length 0x0826 8 v1.1
320 # d-phy spread spectrum control registers
321 PHY_SSC_ctrl 0x0828 8 v1.1
322 - b enable 0
325 manual_LP_ctrl 0x0829 8 v1.1
326 - b enable 0
329 twakeup 0x082a v1.1
330 tinit 0x082b v1.1
331 ths_exit 0x082c v1.1
332 ths_exit_ex 0x082e 16 v1.1
336 - b frame_blanking 0
339 - b stream_start 0
340 DPHY_calibration_mode 0x0833 8 v1.1
341 - b also_alternate 0
342 CPHY_calibration_mode 0x0834 8 v1.1
343 - e format_1 0
344 - e format_2 1
345 - e format_3 2
346 t3_calpreamble_length 0x0835 8 v1.1
347 t3_calpreamble_length_per 0x0836 8 v1.1
348 t3_calaltseq_length 0x0837 8 v1.1
349 t3_calaltseq_length_per 0x0838 8 v1.1
350 FM2_init_seed 0x083a 16 v1.1
351 t3_caludefseq_length 0x083c 16 v1.1
352 t3_caludefseq_length_per 0x083e 16 v1.1
354 # c-phy manual control registers
356 - b preamable_prog_seq 7
357 - f begin_preamble_length 0 5
359 - f post_length 0 4
361 - l n2 0 6 1
362 - f symbol_n_1 3 5
363 - f symbol_n 0 2
369 - b lvlp_dphy 0
370 - b lvlp_cphy 1
371 - b alp_cphy 2
378 TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1
379 TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1
383 - b enabled 0
384 - f 2 3
385 - e 1_seed_cphy 0
386 - e 4_seed_cphy 3
388 - l seed 0 3 0x10
389 - l lane 0 7 0x2
392 TX_USL_REV_ENTRY 0x08c0 16 v1.1
393 TX_USL_REV_Clock_Counter 0x08c2 16 v1.1
394 TX_USL_REV_LP_Counter 0x08c4 16 v1.1
395 TX_USL_REV_Frame_Counter 0x08c6 16 v1.1
396 TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1
397 TX_USL_FWD_ENTRY 0x08ca 16 v1.1
398 TX_USL_GPIO 0x08cc 16 v1.1
399 TX_USL_Operation 0x08ce 16 v1.1
400 - b reset 0
401 TX_USL_ALP_ctrl 0x08d0 16 v1.1
402 - b clock_pause 0
403 TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
404 TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1
405 USL_Clock_Mode_d_ctrl 0x08d2 v1.1
406 - b cont_clock_standby 0
407 - b cont_clock_vblank 1
408 - b cont_clock_hblank 2
417 - b enable 0
418 - b write 1
419 - b clear_error 2
421 - b read_if_ready 0
422 - b write_if_ready 1
423 - b data_corrupted 2
424 - b improper_if_usage 3
427 - l p 0 63 1
431 - b enable 0
434 - b enable 0
436 - b enable 0
438 - b enable 0
440 - b enable 0
442 - b enable 0
444 - b enable 0
446 - b enable 0
448 - b luma 0
449 - b chroma 1
450 - b combined 2
454 - b enable 0
455 - b interleaving 1
468 CFA_conversion_ctrl 0x0ba0 v1.1
469 - b bayer_conversion_enable 0
477 - b continuous 0
478 - b truncate 1
479 - b async 3
482 - b retimed 0
484 - b continuous 0
485 - b truncate 1
486 - b async 3
487 - b adjust_edge 4
493 - b retimed 0
499 - b enable 0
500 - b processed 1
501 - b interleaved 2
502 - b visible_pdaf_correction 3
513 - b continue_streaming 0
514 - b loop_mode 1
516 bracketing_LUT_frame(n) 0x0e10 v1.1 f
517 - l n 0 0xef 1
521 - b fine 0
529 - e none 0
530 - e global 2
536 Pedestal_capability 0x10e0 8 v1.1
540 - b bit_depth_ctrl 0
541 ADC_bit_depth_capability 0x10f4 32 v1.1
561 # video timing set-up capability registers
571 - b lane_speed 0
572 - b link_decoupled 1
573 - b dual_pll_op_sys_ddr 2
574 - b dual_pll_op_pix_ddr 3
577 op_bits_per_lane 0x113b 8 v1.1
588 - b auto_frame_length 0
589 - b rolling_shutter_manual_readout 2
590 - b delayed_exposure_start 3
591 - b manual_exposure_embedded_data 4
595 - e fixed 0
596 - e variable 1
598 # output clock set-up capability registers
618 x_addr_start_div_constant 0x1190 v1.1
619 y_addr_start_div_constant 0x1191 v1.1
620 x_addr_end_div_constant 0x1192 v1.1
621 y_addr_end_div_constant 0x1193 v1.1
622 x_size_div 0x1194 v1.1
623 y_size_div 0x1195 v1.1
624 x_output_div 0x1196 v1.1
625 y_output_div 0x1197 v1.1
626 non_flexible_resolution_support 0x1198 v1.1
627 - b new_pix_addr 0
628 - b new_output_res 1
629 - b output_crop_no_pad 2
630 - b output_size_lane_dep 3
641 - b dual_pll 0
642 - b single_pll 1
643 - b ext_divider 2
644 - b flexible_op_pix_clk_div 3
645 clock_capa_type_capability 0x11b9 v1.1
646 - b ireal 0
648 # sub-sampling parameters limit registers
653 aux_subsamp_capability 0x11c8 v1.1
654 - b factor_power_of_2 1
655 aux_subsamp_mono_capability 0x11c9 v1.1
656 - b factor_power_of_2 1
657 monochrome_capability 0x11ca v1.1
658 - e inc_odd 0
659 - e inc_even 1
660 pixel_readout_capability 0x11cb v1.1
661 - e bayer 0
662 - e monochrome 1
663 - e bayer_and_mono 2
664 min_even_inc_mono 0x11cc 16 v1.1
665 max_even_inc_mono 0x11ce 16 v1.1
666 min_odd_inc_mono 0x11d0 16 v1.1
667 max_odd_inc_mono 0x11d2 16 v1.1
668 min_even_inc_bc2 0x11d4 16 v1.1
669 max_even_inc_bc2 0x11d6 16 v1.1
670 min_odd_inc_bc2 0x11d8 16 v1.1
671 max_odd_inc_bc2 0x11da 16 v1.1
672 min_even_inc_mono_bc2 0x11dc 16 v1.1
673 max_even_inc_mono_bc2 0x11de 16 v1.1
674 min_odd_inc_mono_bc2 0x11f0 16 v1.1
675 max_odd_inc_mono_bc2 0x11f2 16 v1.1
679 - e none 0
680 - e horizontal 1
681 - e reserved 2
687 - e none 0
688 - e input_crop 1
692 - b 2x2_binning 0
693 - b combined_analog_gain 1
694 - b separate_analog_gain 2
695 - b upscaling 3
696 - b reset_sync 4
697 - b direct_short_exp_timing 5
698 - b direct_short_exp_synthesis 6
702 - l n 0 1 1
703 - f row 0 3
704 - f column 4 7
706 - b combined_digital_gain 0
707 - b separate_digital_gain 1
708 - b timing_mode 3
709 - b synthesis_mode 4
713 usl_support_capability 0x1230 v1.1
714 - b clock_tree 0
715 - b rev_clock_tree 1
716 - b rev_clock_calc 2
717 usl_clock_mode_d_capability 0x1231 v1.1
718 - b cont_clock_standby 0
719 - b cont_clock_vblank 1
720 - b cont_clock_hblank 2
721 - b noncont_clock_standby 3
722 - b noncont_clock_vblank 4
723 - b noncont_clock_hblank 5
724 min_op_sys_clk_div_rev 0x1234 v1.1
725 max_op_sys_clk_div_rev 0x1236 v1.1
726 min_op_pix_clk_div_rev 0x1238 v1.1
727 max_op_pix_clk_div_rev 0x123a v1.1
728 min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal
729 max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal
730 min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal
731 max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal
732 max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal
733 max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal
737 - b dpcm_pcm_simple 0
741 - b solid_color 0
742 - b color_bars 1
743 - b fade_to_grey 2
744 - b pn9 3
745 - b color_tile 5
751 - f num_pixels 0 2
752 - b compression 3
753 test_pattern_capability 0x1317 v1.1
754 - b no_repeat 1
755 pattern_size_div_m1 0x1318 v1.1
759 - e none 0
760 - e derating 1
761 - e derating_overrating 2
763 # csi-2 capability registers
765 - b auto_phy_ctl 0
766 - b ui_phy_ctl 1
767 - b dphy_time_ui_reg_1_ctl 2
768 - b dphy_time_ui_reg_2_ctl 3
769 - b dphy_time_ctl 4
770 - b dphy_ext_time_ui_reg_1_ctl 5
771 - b dphy_ext_time_ui_reg_2_ctl 6
772 - b dphy_ext_time_ctl 7
774 - b 1_lane 0
775 - b 2_lane 1
776 - b 3_lane 2
777 - b 4_lane 3
778 - b 5_lane 4
779 - b 6_lane 5
780 - b 7_lane 6
781 - b 8_lane 7
783 - b csi_dphy 2
784 - b csi_cphy 3
786 - e no_frame_truncation 0
787 - e frame_truncation 1
789 - b cci_addr_change 0
790 - b 2nd_cci_addr 1
791 - b sw_changeable_2nd_cci_addr 2
793 - b dpcm_programmable 0
794 - b bottom_embedded_dt_programmable 1
795 - b bottom_embedded_vc_programmable 2
796 - b ext_vc_range 3
798 - b 1_lane 0
799 - b 2_lane 1
800 - b 3_lane 2
801 - b 4_lane 3
802 - b 5_lane 4
803 - b 6_lane 5
804 - b 7_lane 6
805 - b 8_lane 7
806 emb_data_capability 0x1607 v1.1
807 - b two_bytes_per_raw16 0
808 - b two_bytes_per_raw20 1
809 - b two_bytes_per_raw24 2
810 - b no_one_byte_per_raw16 3
811 - b no_one_byte_per_raw20 4
812 - b no_one_byte_per_raw24 5
814 - l n 0 7 4 4,0x32
816 - b supported 0
817 - b CCS_format 1
818 - b reset_0x80 2
820 - l n 0 7 4 4,0x30
822 - b equalization_ctrl 0
823 - b eq1 1
824 - b eq2 2
826 - b equalization_ctrl 0
828 - b preamble_seq_ctrl 0
830 - b supported 0
832 - b manual 0
833 - b manual_streaming 1
834 - b format_1_ctrl 2
835 - b format_2_ctrl 3
836 - b format_3_ctrl 4
838 - b manual 0
839 - b manual_streaming 1
840 - b alternate_seq 2
842 - b tgr_length 0
843 - b tgr_preamble_prog_seq 1
844 - b extra_cphy_manual_timing 2
845 - b clock_based_manual_cdphy 3
846 - b clock_based_manual_dphy 4
847 - b clock_based_manual_cphy 5
848 - b manual_lp_dphy 6
849 - b manual_lp_cphy 7
851 - b pdq_short 0
852 - b spacer_short 1
853 - b pdq_long 2
854 - b spacer_long 3
855 - b spacer_no_pdq 4
857 - b pdq_short_opt1 0
858 - b spacer_short_opt1 1
859 - b pdq_long_opt1 2
860 - b spacer_long_opt1 3
861 - b spacer_short_opt2 4
862 - b spacer_long_opt2 5
863 - b spacer_no_pdq_opt1 6
864 - b spacer_variable_opt2 7
866 - e lvlp_not_supported 0 0x3
867 - e lvlp_supported 1 0x3
868 - e controllable_lvlp 2 0x3
870 - e lvlp_not_supported 0 0x3
871 - e lvlp_supported 1 0x3
872 - e controllable_lvlp 2 0x3
873 - e alp_not_supported 0xc 0xc
874 - e alp_supported 0xd 0xc
875 - e controllable_alp 0xe 0xc
877 - b scrambling_supported 0
878 - f max_seeds_per_lane_c 1 2
879 - e 1 0
880 - e 4 3
881 - f num_seed_regs 3 5
882 - e 0 0
883 - e 1 1
884 - e 4 4
885 - b num_seed_per_lane 6
888 CSI2_interface_capability_misc 0x1639 v1.1
889 - b eotp_short_pkt_opt2 0
890 PHY_ctrl_capability_3 0x165c v1.1
891 - b dphy_timing_not_multiple 0
892 - b dphy_min_timing_value_1 1
893 - b twakeup_supported 2
894 - b tinit_supported 3
895 - b ths_exit_supported 4
896 - b cphy_timing_not_multiple 5
897 - b cphy_min_timing_value_1 6
898 dphy_sf 0x165d v1.1
899 cphy_sf 0x165e v1.1
900 - f twakeup 0 3
901 - f tinit 4 7
902 dphy_limits_1 0x165f v1.1
903 - f ths_prepare 0 3
904 - f ths_zero 4 7
905 dphy_limits_2 0x1660 v1.1
906 - f ths_trail 0 3
907 - f tclk_trail_min 4 7
908 dphy_limits_3 0x1661 v1.1
909 - f tclk_prepare 0 3
910 - f tclk_zero 4 7
911 dphy_limits_4 0x1662 v1.1
912 - f tclk_post 0 3
913 - f tlpx 4 7
914 dphy_limits_5 0x1663 v1.1
915 - f ths_exit 0 3
916 - f twakeup 4 7
917 dphy_limits_6 0x1664 v1.1
918 - f tinit 0 3
919 cphy_limits_1 0x1665 v1.1
920 - f t3_prepare_max 0 3
921 - f t3_lpx_max 4 7
922 cphy_limits_2 0x1666 v1.1
923 - f ths_exit_max 0 3
924 - f twakeup_max 4 7
925 cphy_limits_3 0x1667 v1.1
926 - f tinit_max 0 3
937 - e unsupported 0
938 - e binning_then_subsampling 1
939 - e subsampling_then_binning 2
941 - b averaged 0
942 - b summed 1
943 - b bayer_corrected 2
944 - b module_specific_weight 3
947 - l n 0 63 1
948 - f row 0 3
949 - f column 4 7
950 binning_weighting_mono_capability 0x1771 v1.1
951 - b averaged 0
952 - b summed 1
953 - b bayer_corrected 2
954 - b module_specific_weight 3
955 binning_sub_types_mono 0x1772 v1.1
956 binning_sub_type_mono(n) 0x1773 v1.1 f
957 - l n 0 63 1
961 - b supported 0
962 - b polling 2
966 - b color_shading 0
967 - b luminance_correction 1
969 - b supported 0
972 - b mapped_defect 0
973 - b dynamic_couplet 2
974 - b dynamic_single 5
975 - b combined_dynamic 8
977 - b dynamic_triplet 3
979 - b luma 0
980 - b chroma 1
981 - b combined 2
985 - b controllable_readout 0
986 - b visible_pixel_readout 1
987 - b different_vc_readout 2
988 - b different_dt_readout 3
989 - b prog_data_format 4
993 - b kelvin 0
994 - b awb_gain 1
997 CFA_pattern_capability 0x1990 v1.1
998 - e bayer 0
999 - e monochrome 1
1000 - e 4x4_quad_bayer 2
1001 - e vendor_specific 3
1002 CFA_pattern_conversion_capability 0x1991 v1.1
1003 - b bayer 0
1007 - b single_strobe 0
1009 - b fixed_width 0
1010 - b edge_ctrl 1
1013 reset_max_delay 0x1a10 v1.1
1014 reset_min_time 0x1a11 v1.1
1018 - b supported 0
1019 - b processed_bottom_embedded 1
1020 - b processed_interleaved 2
1021 - b raw_bottom_embedded 3
1022 - b raw_interleaved 4
1023 - b visible_pdaf_correction 5
1024 - b vc_interleaving 6
1025 - b dt_interleaving 7
1027 - b ROI 0
1028 - b after_digital_crop 1
1029 - b ctrl_retimed 2
1033 - b coarse_integration 0
1034 - b global_analog_gain 1
1035 - b flash 4
1036 - b global_digital_gain 5
1037 - b alternate_global_analog_gain 6
1039 - b single_bracketing_mode 0
1040 - b looped_bracketing_mode 1