driver-api/gpio/driver.rst

2 GPIO Driver Interface
5 This document serves as a guide for writers of GPIO chip drivers.
7 Each GPIO controller driver needs to include the following header, which defines
8 the structures used to define a GPIO driver::
16 A GPIO chip handles one or more GPIO lines. To be considered a GPIO chip, the
18 line is not general purpose, it is not GPIO and should not be handled by a
19 GPIO chip. The use case is the indicative: certain lines in a system may be
20 called GPIO but serve a very particular purpose thus not meeting the criteria
22 GPIO and should therefore still be handled by a GPIO chip driver.
24 Inside a GPIO driver, individual GPIO lines are identified by their hardware
28 The hardware GPIO number should be something intuitive to the hardware, for
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
34 This number is purely internal: the hardware number of a particular GPIO
37 On top of this internal number, each GPIO line also needs to have a global
38 number in the integer GPIO namespace so that it can be used with the legacy GPIO
40 assigned), and for each GPIO line the global number will be (base + hardware
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
55 In the gpiolib framework each GPIO controller is packaged as a "struct
60  - methods to establish GPIO line direction
61  - methods used to access GPIO line values
62  - method to set electrical configuration for a given GPIO line
63  - method to return the IRQ number associated to a given GPIO line
68  - optional label for diagnostics and GPIO chip mapping using platform data
73 a GPIO controller should be rare; use gpiochip_remove() when it is unavoidable.
76 exposed by the GPIO interfaces, such as addressing, power management, and more.
77 Chips such as audio codecs will have complex non-GPIO states.
81 NULL or the label associated with that GPIO line when it was requested.
83 Realtime considerations: the GPIO driver should not use spinlock_t or any
85 and direction control callbacks) if it is expected to call GPIO APIs from
90 GPIO electrical configuration
93 GPIO lines can be configured for several electrical modes of operation by using
106 ending up in the pin control back-end "behind" the GPIO controller, usually
108 listed GPIO configurations.
110 If a pin controller back-end is used, the GPIO controller or hardware
111 description needs to provide "GPIO ranges" mapping the GPIO line offsets to pin
115 GPIO lines with debounce support
132 GPIO lines with open drain/source support
153 - Inverse wire-OR on an I/O line, for example a GPIO line, making it possible
184 The desired output signal (e.g. coming directly from some GPIO output register)
195 Some GPIO hardware come in open drain / open source configuration. Some are
215 If this state can not be configured in hardware, i.e. if the GPIO hardware does
216 not support open drain/open source in hardware, the GPIO library will instead
229 GPIO lines with pull up/down resistor support
232 A GPIO line can support pull-up/down using the .set_config() callback. This
234 GPIO line, and this resistor is software controlled.
245 If the GPIO line supports shunting in different resistance values for the
246 pull-up or pull-down resistor, the GPIO chip callback .set_config() will not
247 suffice. For these complex use cases, a combined GPIO chip and pin controller
253 GPIO drivers providing IRQs
256 It is custom that GPIO drivers (GPIO chips) are also providing interrupts,
258 cases the GPIO logic is melded with a SoC's primary interrupt controller.
260 The IRQ portions of the GPIO block are implemented using an irq_chip, using
265 is a combined GPIO+IRQ driver. The basic premise is that gpio_chip and
270 certain GPIO line and should not be relied upon to have been called before
274 callbacks from the GPIO and irq_chip APIs. Do not rely on gpiod_to_irq() having
277 We can divide GPIO irqchips in two broad categories:
279 - CASCADED INTERRUPT CHIPS: this means that the GPIO chip has one common
280   interrupt output line, which is triggered by any enabled GPIO line on that
284   inside the GPIO controller to figure out which line fired it. The irqchip
292 - HIERARCHICAL INTERRUPT CHIPS: this means that each GPIO line has a dedicated
294   to inquire the GPIO hardware to figure out which line has fired, but it
298 Realtime considerations: a realtime compliant GPIO driver should not use
308 Cascaded GPIO irqchips
311 Cascaded GPIO irqchips usually fall in one of three categories:
313 - CHAINED CASCADED GPIO IRQCHIPS: these are usually the type that is embedded on
316   system interrupt controller. This means that the GPIO irqchip handler will
318   disabled. The GPIO irqchip will then end up calling something like this
326   Chained GPIO irqchips typically can NOT set the .can_sleep flag on
334   If required (and if it can't be converted to the nested threaded GPIO irqchip,
351 - GENERIC CHAINED GPIO IRQCHIPS: these are the same as "CHAINED GPIO irqchips",
352   but chained IRQ handlers are not used. Instead GPIO IRQs dispatching is
354   The GPIO irqchip will then end up calling something like this sequence in
358         for each detected GPIO IRQ
363   with IRQ enabled and the same work-around as for "CHAINED GPIO irqchips" can
366 - NESTED THREADED GPIO IRQCHIPS: these are off-chip GPIO expanders and any
367   other GPIO irqchip residing on the other side of a sleeping bus such as I2C
381   The hallmark of threaded GPIO irqchips is that they set the .can_sleep
389 Infrastructure helpers for GPIO irqchips
392 To help out in handling the set-up and management of GPIO irqchips and the
398 GPIO line index:
401     :header: GPIO line offset, Hardware IRQ
410 If some GPIO lines do not have corresponding IRQs, the bitmask valid_mask
417 same time as setting up the rest of the GPIO functionality. The following
649 If there is a need to exclude certain GPIO lines from the IRQ domain handled by
652 .irq.valid_mask with as many bits set as there are GPIO lines in the chip, each
653 bit representing line 0..n-1. Drivers can exclude GPIO lines by clearing bits
672 Since GPIO and irq_chip are orthogonal, we can get conflicts between different
673 use cases. For example a GPIO line used for IRQs should be an input line,
674 it does not make sense to fire interrupts on an output GPIO.
677 resource (a certain GPIO line and register for example) it needs to deny
681 to mark the GPIO as being used as an IRQ::
685 This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
690 When implementing an irqchip inside a GPIO driver, these two functions should
701 In some (fringe) use cases, a driver may be using a GPIO line as input for IRQs,
706 When a GPIO is used as an IRQ signal, then gpiolib also needs to know if
712 This allows drivers to drive the GPIO as an output while the IRQ is
717 When implementing an irqchip inside a GPIO driver, these two functions should
726 Real-Time compliance for GPIO IRQ chips
730 preemption. It is desirable that all irqchips in the GPIO subsystem keep this
742 - Chained GPIO irqchips: ensure spinlock_t or any sleepable APIs are not used
744 - Generic chained GPIO irqchips: take care about generic_handle_irq() calls and
746 - Chained GPIO irqchips: get rid of the chained IRQ handler and use generic irq
749   .disable_locking and handling the locking in the GPIO driver
758 Requesting self-owned GPIO pins
761 Sometimes it is useful to allow a GPIO chip driver to request its own GPIO
762 descriptors through the gpiolib API. A GPIO driver can use the following