Documentation/driver-api/edac.rst

5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
35 * Channel
37 A memory controller channel, responsible to communicate with a group of
38 DIMMs. Each channel has its own independent control (command) and data
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
48 just one memory stick when an error occurs, as the error correction code
49 is calculated using two DIMMs instead of one. Due to that, it is capable
52 * Single-channel
54 The data accessed by the memory controller is contained into one dimm
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56 one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
71 dual channel 128 bits. It may not be visible by the memory controller,
75 * Single-Ranked stick
77 A Single-ranked stick has 1 chip-select row of memory. Motherboards
78 commonly drive two chip-select pins to a memory stick. A single-ranked
79 stick, will occupy only one of those rows. The other will be unused.
83 * Double-Ranked stick
85 A double-ranked stick has two chip-select rows which access different
88 * Double-sided stick
90 **DEPRECATED TERM**, see :ref:`Double-Ranked stick <doubleranked>`.
92 A double-sided stick has two chip-select rows which access different sets
94 "Double-sided" is irrespective of the memory devices being mounted on
100 all of the memory sticks spanned by a chip-select row.  A single socket
101 set has two chip-select rows and if double-sided sticks are used these
102 will occupy those chip-select rows.
107 between chip-select rows and socket sets.
111 HBM is a new memory type with low power consumption and ultra-wide
113 interconnected by microscopic wires called "through-silicon vias," or
116 Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
118 are nearly indistinguishable from on-chip integrated RAM.
121 ------------------
128 .. kernel-doc:: include/linux/edac.h
130 .. kernel-doc:: drivers/edac/edac_mc.h
133 ---------------
139 .. kernel-doc:: drivers/edac/edac_pci.h
142 -----------
155 - CPU caches (L1 and L2)
156 - DMA engines
157 - Core CPU switches
158 - Fabric switch units
159 - PCIe interface controllers
160 - other EDAC/ECC type devices that can be monitored for
175 		/L1-cache/ce_count
177 		/L2-cache/ce_count
180 		/L1-cache/ce_count
182 		/L2-cache/ce_count
188 .. kernel-doc:: drivers/edac/edac_device.h
192 ----------------------------
200 Each UMC contains eight channels. Each UMC channel controls one 128-bit
201 HBM2e (2GB) channel (equivalent to 8 X 2GB ranks).  This creates a total
202 of 4096-bits of DRAM data bus.
205 channel is interfacing 2GB of DRAM (represented as rank).
209 	GPU DF / GPU Node -> EDAC MC
210 	GPU UMC           -> EDAC CSROW
211 	GPU UMC channel   -> EDAC CHANNEL
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
221 - CPU UMCs use 1 channel, In this case UMC = EDAC channel. This follows the
223 - CPU UMCs use up to 4 chip selects, So UMC chip select = EDAC CSROW.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
235 		mc0   - CPU MC node 0
237 		mc2  |- GPU card[0] => node 0(mc1), node 1(mc2)
239 		mc4  |- GPU card[1] => node 0(mc3), node 1(mc4)
241 		mc6  |- GPU card[2] => node 0(mc5), node 1(mc6)
243 		mc8  |- GPU card[3] => node 0(mc7), node 1(mc8)
245 For example, a heterogeneous system with one AMD CPU is connected to
258 	│   │   ├── channel 0	# Each UMC has 8 channels
259 	│   │   ├── channel 1   # size of each channel is 2 GB, so each UMC has 16 GB
260 	│   │   ├── channel 2
261 	│   │   ├── channel 3
262 	│   │   ├── channel 4
263 	│   │   ├── channel 5
264 	│   │   ├── channel 6
265 	│   │   ├── channel 7
267 	│   │   ├── channel 0
269 	│   │   ├── channel 7
272 	│   │   ├── channel 0
274 	│   │   ├── channel 7